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* Remove isValidBelForCellgatecat2021-02-162-11/+0
| | | | | | | | | | | | | | | | | This Arch API dates from when we were first working out how to implement placement validity checking, and in practice is little used by the core parts of placer1/HeAP and the Arch implementation involves a lot of duplication with isBelLocationValid. In the short term; placement validity checking is better served by the combination of checkBelAvail and isValidBelForCellType before placement; followed by isBelLocationValid after placement (potentially after moving/swapping multiple cells). Longer term, removing this API makes things a bit cleaner for a new validity checking API. Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #575 from YosysHQ/gatecat/belpin-2gatecat2021-02-151-1/+1
|\ | | | | Support for cell pin to bel pin mappings
| * Start making use of getBelPinsForCellPin APIgatecat2021-02-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This replaces getNetinfoSinkWire with 3 new functions for different use cases. At the moment all existing code has been moved to getNetinfoSinkWire with phys_idx=0 so the build doesn't break; but this won't yet function properly with more than one sink. But it provides a base on which to work on refactoring the routers to support this case. Signed-off-by: gatecat <gatecat@ds0.me>
* | Add getBelHidden and add some missing "override" statements.Keith Rothman2021-02-111-1/+1
|/ | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add BaseArchRanges for default ArchRanges typesgatecat2021-02-091-16/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #568 from YosysHQ/dave/arch-overridegatecat2021-02-085-303/+106
|\ | | | | Create a new BaseArch that formally specifies the Arch API and provides some base implementations
| * Use 'T' postfix to disambiguate LHS and RHS of usingD. Shah2021-02-081-21/+21
| | | | | | | | | | | | | | Arches might otherwise have range types named ambigiously with the entry in ArchRanges. Signed-off-by: D. Shah <dave@ds0.me>
| * Add archArgs and archArgsToId to Arch APID. Shah2021-02-051-2/+3
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
| * nexus: Switch to BaseArchD. Shah2021-02-055-301/+103
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
* | Use RelSlice::ssize instead of cast-to-int throughoutD. Shah2021-02-081-10/+10
|/ | | | Signed-off-by: D. Shah <dave@ds0.me>
* Mark IdString and IdStringList single argument constructors explicit.Keith Rothman2021-02-045-16/+16
| | | | | | | | | Single argument constructors will silently convert to that type. This is typically not the right thing to do. For example, the nexus and ice40 arch_pybindings.h files were incorrectly parsing bel name strings, etc. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* nexus: Implement IdStringList for all arch object namesD. Shah2021-02-023-59/+56
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* arch: Add getNameDelimiter API for string listsD. Shah2021-02-021-0/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Run "make clangformat".Keith Rothman2021-02-024-27/+21
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add pybindings for new APIs.Keith Rothman2021-02-022-0/+15
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Rename Partition -> BelBucket.Keith Rothman2021-02-023-29/+29
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add Partition APIs to ice40, nexus, gowin archs.Keith Rothman2021-02-023-2/+80
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial refactoring of placer API.Keith Rothman2021-02-021-0/+5
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Seperate PipRange types in pybindings_shared.Keith Rothman2021-02-012-2/+2
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* cleanup: Spelling fixesD. Shah2021-01-281-1/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* cleanup: Fix compiler warningsD. Shah2021-01-281-2/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Make RelSlice uncopyableD. Shah2021-01-271-1/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Move RelPtr/RelSlice out of arches into commonD. Shah2021-01-271-39/+1
| | | | | | | The bba approach seems widely used enough that it's reasonable for this to become part of common code. Signed-off-by: D. Shah <dave@ds0.me>
* nexus: Switch from RelPtr to RelSliceD. Shah2021-01-274-127/+113
| | | | | | | | | | This replaces RelPtrs and a separate length field with a Rust-style slice containing both a pointer and a length; with bounds checking always enforced. Thus iterating over these structures is both cleaner and safer. Signed-off-by: D. Shah <dave@ds0.me>
* nexus: Add MULTADDSUB9X9WIDE supportDavid Shah2020-12-082-28/+71
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Fix LRAM pin typesDavid Shah2020-12-072-10/+11
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Add support for initialised LRAMDavid Shah2020-12-074-12/+50
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Add basic LRAM support (no init)David Shah2020-12-026-4/+116
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Add PLL supportDavid Shah2020-12-024-3/+213
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Add support for deriving timing constraints in packerDavid Shah2020-12-021-0/+96
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus/pdc: Parse simple clock constraintsDavid Shah2020-12-021-0/+61
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Fix db integrity checkDavid Shah2020-11-302-18/+7
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Add post-place LUTFF optimisationDavid Shah2020-11-304-19/+200
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Improve error handling in global routerDavid Shah2020-11-301-0/+8
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Preliminary integration of DSP timing dataDavid Shah2020-11-303-4/+111
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Tweak heuristics to improve routeabilityDavid Shah2020-11-301-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Clocked MULTADDSUB36X36 fixDavid Shah2020-11-301-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Add MULTADDSUB36X36David Shah2020-11-301-4/+21
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Add MULTADDSUB18X18 supportDavid Shah2020-11-302-17/+78
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: ACC54 definitionsDavid Shah2020-11-303-0/+77
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Add DSP pre-adder supportDavid Shah2020-11-302-2/+23
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Fix DSP signed portsDavid Shah2020-11-301-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Larger DSP tweaksDavid Shah2020-11-302-9/+15
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Fix slow routing around DSPsDavid Shah2020-11-302-0/+28
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Fix validity checking when DSPs are usedDavid Shah2020-11-302-3/+10
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Refactor DSP macro splitting to make it more genericDavid Shah2020-11-303-29/+139
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Add support for clocked MULT9X9sDavid Shah2020-11-302-0/+45
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Support for unclocked 9x9 multipliesDavid Shah2020-11-303-13/+96
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: More DSP primitive configDavid Shah2020-11-303-1/+67
| | | | Signed-off-by: David Shah <dave@ds0.me>
* nexus: Miscellaneous DSP infrastructureDavid Shah2020-11-302-0/+125
| | | | Signed-off-by: David Shah <dave@ds0.me>
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