| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | run clangformat | gatecat | 2022-02-03 | 1 | -2/+1 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Fixed correction of Nexus OSCA frequency constraints | Maciej Kurc | 2022-02-02 | 1 | -2/+2 |
| | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | nexus: add option to modify the mult factor of the estimate delay | Alessandro Comodi | 2022-02-01 | 3 | -1/+11 |
| | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | Added honoring OSCA output frequency tolerance during constraints generation | Maciej Kurc | 2022-01-28 | 1 | -2/+3 |
| | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Removed the need for MULT36_CORE bel for implementing the MULTADDSUB9X9WIDE ↵ | Maciej Kurc | 2022-01-25 | 1 | -1/+1 |
| | | | | | | | macro Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | nexus: handle SLEWRATE in pdc | Karol Gugala | 2021-12-20 | 3 | -2/+10 |
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| * | archapi: Use arbitrary rather than actual placement in predictDelay | gatecat | 2021-12-19 | 2 | -8/+6 |
| | | | | | | | | | | | | | This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | nexus: router1 speedup based on #867 | gatecat | 2021-12-17 | 2 | -2/+73 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | clangformat | gatecat | 2021-12-12 | 2 | -16/+13 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Added checking if all FFs added to an existing cluster have matching ↵ | Maciej Kurc | 2021-11-23 | 1 | -0/+44 |
| | | | | | | | configuration Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Fixed potential issues with carry-chain cluster expansion, added a parameter ↵ | Maciej Kurc | 2021-11-22 | 2 | -14/+23 |
| | | | | | | | controlling the ratio of FFs that got glued to carry-chain clusters. Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Added appending FFs to other existing LUT cluster types (carry, widefn) | Maciej Kurc | 2021-11-22 | 1 | -18/+67 |
| | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Added an option to control LUT and FF packing | Maciej Kurc | 2021-11-22 | 2 | -1/+8 |
| | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Added clustering free LUTs and FFs | Maciej Kurc | 2021-11-22 | 1 | -0/+73 |
| | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | nexus: Add resource cost overrides | gatecat | 2021-09-24 | 2 | -2/+21 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | nexus: LUT permutation support | gatecat | 2021-09-24 | 4 | -4/+72 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Merge pull request #822 from YosysHQ/gatecat/nexus-split-vcc | gatecat | 2021-09-23 | 3 | -0/+7 |
| |\ | | | | | nexus: Support for split Vcc routing | ||||
| | * | nexus: Support for split Vcc routing | gatecat | 2021-09-22 | 3 | -0/+7 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | | Merge pull request #823 from YosysHQ/gatecat/nexus-r1-tweaks | gatecat | 2021-09-22 | 2 | -2/+4 |
| |\ \ | | | | | | | nexus: Tweaks for router1 performance | ||||
| | * | | nexus: Tweaks for router1 performance | gatecat | 2021-09-22 | 2 | -2/+4 |
| | |/ | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * / | nexus: Fix DSP macro placement | gatecat | 2021-09-22 | 4 | -32/+80 |
| |/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Added support for syn_useioff for enabling tri-state control FF integration ↵ | Maciej Kurc | 2021-09-20 | 1 | -13/+23 |
| | | | | | | | into IOLOGIC. Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Use correct names for IDDRX1_ODDRX1 FASM features | Maciej Kurc | 2021-09-17 | 2 | -22/+4 |
| | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Added automatic inference and integration of FFs driving T pin into IOLOGIC | Maciej Kurc | 2021-09-17 | 2 | -16/+177 |
| | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Added handling of the case when tri-state control net bypasses SIOLOGIC bel | Maciej Kurc | 2021-09-17 | 1 | -2/+81 |
| | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | nexus: Fix getBelGlobalBuf | gatecat | 2021-09-02 | 1 | -1/+5 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | nexus: Fix routeing of global clocks that also drive fabric | gatecat | 2021-07-28 | 1 | -2/+35 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | nexus: Basic packer and FASM support for I/ODDR | gatecat | 2021-07-28 | 4 | -2/+124 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | nexus: Add IOLOGIC pins data | gatecat | 2021-07-28 | 3 | -2/+30 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | nexus: Disable center DCC-thrus on 17k device | gatecat | 2021-06-16 | 3 | -1/+29 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | nexus: Fix FASM gen for DCC-thru | gatecat | 2021-06-16 | 1 | -3/+34 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Fixing old emails and names in copyrights | gatecat | 2021-06-12 | 14 | -15/+15 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | nexus: Fix LRAM x coord | gatecat | 2021-06-10 | 1 | -0/+2 |
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| * | Remove redundant code after hashlib move | gatecat | 2021-06-02 | 1 | -61/+0 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Use hashlib in most remaining code | gatecat | 2021-06-02 | 1 | -2/+2 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Using hashlib in arches | gatecat | 2021-06-02 | 8 | -49/+47 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Use hashlib for core netlist structures | gatecat | 2021-06-02 | 6 | -62/+62 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Add hash() member functions | gatecat | 2021-06-02 | 1 | -0/+6 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | router2: Add heatmap by routing resource type | gatecat | 2021-05-20 | 3 | -0/+15 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Revert "nexus: Enable placeAllAtOnce" | gatecat | 2021-05-06 | 1 | -1/+4 |
| | | | | | This reverts commit 0abe425675ae0cc550194171f1f15ec4058a05d6. | ||||
| * | nexus: Use new cluster API | gatecat | 2021-05-06 | 3 | -13/+17 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | nexus: Enable placeAllAtOnce | gatecat | 2021-04-25 | 1 | -4/+1 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | nexus: Fix some IO FASM gen | gatecat | 2021-03-30 | 1 | -0/+4 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | nexus: Fix LIFCL-17 LRAM FASM | gatecat | 2021-03-30 | 1 | -0/+2 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | nexus: Fix default IO config | gatecat | 2021-03-29 | 1 | -0/+2 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Merge pull request #651 from YosysHQ/gatecat/nexus-vcco | gatecat | 2021-03-29 | 1 | -3/+51 |
| |\ | | | | | nexus: Fix bank Vcco FASM | ||||
| | * | nexus: Fix bank Vcco FASM | gatecat | 2021-03-29 | 1 | -3/+51 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | | nexus: Default HF_OSC_EN to ENABLED | gatecat | 2021-03-29 | 1 | -1/+1 |
| |/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | nexus: Fix FASM gen for LIFCL-17 | gatecat | 2021-03-26 | 1 | -1/+4 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | nexus: Add support for get_pins PDC command | gatecat | 2021-03-25 | 1 | -7/+56 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
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index : iCE40/nextpnr | |
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