From 1436ae21a2d9a214f7585deb2f038ff87ce4862c Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 20 Jun 2018 11:44:28 +0200 Subject: Adding stubs for delay annotation and cell timing lookup Signed-off-by: David Shah --- common/nextpnr.h | 10 +++++----- common/timing.cc | 29 +++++++++++++++++++++++++++++ common/timing.h | 28 ++++++++++++++++++++++++++++ dummy/arch.cc | 18 ++++++++++++++++++ dummy/arch.h | 7 +++++++ frontend/json/jsonparse.cc | 2 +- ice40/arch.cc | 21 +++++++++++++++++++++ ice40/arch.h | 10 ++++++++++ 8 files changed, 119 insertions(+), 6 deletions(-) create mode 100644 common/timing.cc create mode 100644 common/timing.h diff --git a/common/nextpnr.h b/common/nextpnr.h index c59b401e..5ccbf057 100644 --- a/common/nextpnr.h +++ b/common/nextpnr.h @@ -17,13 +17,13 @@ * */ +#include #include #include #include #include #include #include -#include #ifndef NEXTPNR_H #define NEXTPNR_H @@ -196,12 +196,12 @@ struct CellInfo; enum PlaceStrength { - STRENGTH_NONE = 0, - STRENGTH_WEAK = 1, + STRENGTH_NONE = 0, + STRENGTH_WEAK = 1, STRENGTH_STRONG = 2, - STRENGTH_FIXED = 3, + STRENGTH_FIXED = 3, STRENGTH_LOCKED = 4, - STRENGTH_USER = 5 + STRENGTH_USER = 5 }; struct PortRef diff --git a/common/timing.cc b/common/timing.cc new file mode 100644 index 00000000..352ca94a --- /dev/null +++ b/common/timing.cc @@ -0,0 +1,29 @@ +/* + * nextpnr -- Next Generation Place and Route + * + * Copyright (C) 2018 David Shah + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "timing.h" +#include "log.h" +#include +#include +#include + +void assign_budget(Context *ctx, float default_clock = 12e6) +{ + +} diff --git a/common/timing.h b/common/timing.h new file mode 100644 index 00000000..da0cdd9c --- /dev/null +++ b/common/timing.h @@ -0,0 +1,28 @@ +/* + * nextpnr -- Next Generation Place and Route + * + * Copyright (C) 2018 David Shah + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef TIMING_H +#define TIMING_H + +#include "nextpnr.h" + +// Assign "budget" values for all user ports in the design +void assign_budget(Context *ctx, float default_clock = 12e6); + +#endif TIMING_H diff --git a/dummy/arch.cc b/dummy/arch.cc index fb54c74f..64841374 100644 --- a/dummy/arch.cc +++ b/dummy/arch.cc @@ -176,4 +176,22 @@ std::vector Arch::getPipGraphics(PipId pip) const return ret; } +// --------------------------------------------------------------- + +delay_t Arch::getCellDelay(const CellInfo *cell, IdString fromPort, + IdString toPort) const +{ + return 0; +} + +IdString Arch::getPortClock(const CellInfo *cell, IdString port) const +{ + return IdString(); +} + +bool Arch::isClockPort(const CellInfo *cell, IdString port) const +{ + return false; +} + NEXTPNR_NAMESPACE_END diff --git a/dummy/arch.h b/dummy/arch.h index 02bec23a..61a09e00 100644 --- a/dummy/arch.h +++ b/dummy/arch.h @@ -32,7 +32,9 @@ struct DelayInfo delay_t delay = 0; delay_t raiseDelay() const { return delay; } + delay_t fallDelay() const { return delay; } + delay_t avgDelay() const { return delay; } DelayInfo operator+(const DelayInfo &other) const @@ -131,6 +133,11 @@ struct Arch : BaseCtx std::unordered_set belGraphicsReload; std::unordered_set wireGraphicsReload; std::unordered_set pipGraphicsReload; + + delay_t getCellDelay(const CellInfo *cell, IdString fromPort, + IdString toPort) const; + IdString getPortClock(const CellInfo *cell, IdString port) const; + bool isClockPort(const CellInfo *cell, IdString port) const; }; NEXTPNR_NAMESPACE_END diff --git a/frontend/json/jsonparse.cc b/frontend/json/jsonparse.cc index afd126fd..8f0ecc35 100644 --- a/frontend/json/jsonparse.cc +++ b/frontend/json/jsonparse.cc @@ -26,8 +26,8 @@ #include #include #include -#include #include +#include #include "nextpnr.h" NEXTPNR_NAMESPACE_BEGIN diff --git a/ice40/arch.cc b/ice40/arch.cc index ba372410..380f3386 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -416,4 +416,25 @@ std::vector Arch::getPipGraphics(PipId pip) const return ret; } +// ----------------------------------------------------------------------- + +delay_t Arch::getCellDelay(const CellInfo *cell, IdString fromPort, + IdString toPort) const +{ + // TODO + return 0; +} + +IdString Arch::getPortClock(const CellInfo *cell, IdString port) const +{ + // TODO + return IdString(); +} + +bool Arch::isClockPort(const CellInfo *cell, IdString port) const +{ + // TODO + return false; +} + NEXTPNR_NAMESPACE_END diff --git a/ice40/arch.h b/ice40/arch.h index c1256a41..172541c0 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -755,6 +755,16 @@ struct Arch : BaseCtx std::unordered_set belGraphicsReload; std::unordered_set wireGraphicsReload; std::unordered_set pipGraphicsReload; + + // ------------------------------------------------- + + // Get the delay through a cell from one port to another + delay_t getCellDelay(const CellInfo *cell, IdString fromPort, + IdString toPort) const; + // Get the associated clock to a port, or empty if the port is combinational + IdString getPortClock(const CellInfo *cell, IdString port) const; + // Return true if a port is a clock + bool isClockPort(const CellInfo *cell, IdString port) const; }; NEXTPNR_NAMESPACE_END -- cgit v1.2.3