From 174848b4b3bb84883c1623315ad10fdb5eb5185c Mon Sep 17 00:00:00 2001
From: Adam Greig <adam@adamgreig.com>
Date: Wed, 9 Nov 2022 02:44:37 +0000
Subject: Include ALU54B in cell types with wire location overrides

---
 ecp5/arch_place.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ecp5/arch_place.cc b/ecp5/arch_place.cc
index 3151cc3e..30ae9b1b 100644
--- a/ecp5/arch_place.cc
+++ b/ecp5/arch_place.cc
@@ -203,7 +203,7 @@ void Arch::setup_wire_locations()
         CellInfo *ci = cell.second.get();
         if (ci->bel == BelId())
             continue;
-        if (ci->type.in(id_MULT18X18D, id_DCUA, id_DDRDLL, id_DQSBUFM, id_EHXPLLL)) {
+        if (ci->type.in(id_ALU54B, id_MULT18X18D, id_DCUA, id_DDRDLL, id_DQSBUFM, id_EHXPLLL)) {
             for (auto &port : ci->ports) {
                 if (port.second.net == nullptr)
                     continue;
-- 
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