From fc7490370b3f81c4b0285fee545142aeb106979b Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 18 Jun 2018 11:43:59 +0200 Subject: Improving code style and fixing dummy Signed-off-by: David Shah --- common/place_sa.cc | 31 ++++++++++++++++++++----------- dummy/arch_place.cc | 5 +++++ dummy/arch_place.h | 3 +++ frontend/json/jsonparse.cc | 7 ++++--- ice40/cells.cc | 3 ++- 5 files changed, 34 insertions(+), 15 deletions(-) diff --git a/common/place_sa.cc b/common/place_sa.cc index a0c32c1d..6012adf8 100644 --- a/common/place_sa.cc +++ b/common/place_sa.cc @@ -135,6 +135,7 @@ struct SAState bool improved = false; int n_move, n_accept; int diameter = 35; + std::unordered_map bel_types; std::vector>>> fast_bels; std::unordered_set locked_bels; }; @@ -267,7 +268,6 @@ BelId random_bel_for_cell(Design *design, CellInfo *cell, SAState &state, BelId best_bel = BelId(); Chip &chip = design->chip; BelType targetType = belTypeFromId(cell->type); - assert(int(targetType) < state.fast_bels.size()); int x = 0, y = 0; chip.estimatePosition(cell->bel, x, y); while (true) { @@ -275,11 +275,12 @@ BelId random_bel_for_cell(Design *design, CellInfo *cell, SAState &state, int(x) + state.diameter + 1); int ny = random_int_between(rnd, std::max(int(y) - state.diameter, 0), int(y) + state.diameter + 1); - if (nx >= state.fast_bels.at(int(targetType)).size()) + int beltype_idx = state.bel_types.at(targetType); + if (nx >= state.fast_bels.at(beltype_idx).size()) continue; - if (ny >= state.fast_bels.at(int(targetType)).at(nx).size()) + if (ny >= state.fast_bels.at(beltype_idx).at(nx).size()) continue; - const auto &fb = state.fast_bels.at(int(targetType)).at(nx).at(ny); + const auto &fb = state.fast_bels.at(beltype_idx).at(nx).at(ny); if (fb.size() == 0) continue; BelId bel = fb.at(random_int_between(rnd, 0, fb.size())); @@ -343,19 +344,27 @@ void place_design_sa(Design *design, int seed) } // Build up a fast position/type to Bel lookup table int max_x = 0, max_y = 0; + int bel_types = 0; for (auto bel : design->chip.getBels()) { int x, y; design->chip.estimatePosition(bel, x, y); BelType type = design->chip.getBelType(bel); - if (state.fast_bels.size() < int(type) + 1) - state.fast_bels.resize(int(type) + 1); - if (state.fast_bels.at(int(type)).size() < int(x) + 1) - state.fast_bels.at(int(type)).resize(int(x) + 1); - if (state.fast_bels.at(int(type)).at(int(x)).size() < int(y) + 1) - state.fast_bels.at(int(type)).at(int(x)).resize(int(y) + 1); + int type_idx; + if (state.bel_types.find(type) == state.bel_types.end()) { + type_idx = bel_types++; + state.bel_types[type] = type_idx; + } else { + type_idx = state.bel_types.at(type); + } + if (state.fast_bels.size() < type_idx + 1) + state.fast_bels.resize(type_idx + 1); + if (state.fast_bels.at(type_idx).size() < int(x) + 1) + state.fast_bels.at(type_idx).resize(int(x) + 1); + if (state.fast_bels.at(type_idx).at(int(x)).size() < int(y) + 1) + state.fast_bels.at(type_idx).at(int(x)).resize(int(y) + 1); max_x = std::max(max_x, int(x)); max_y = std::max(max_y, int(y)); - state.fast_bels.at(int(type)).at(int(x)).at(int((y))).push_back(bel); + state.fast_bels.at(type_idx).at(int(x)).at(int((y))).push_back(bel); } state.diameter = std::max(max_x, max_y) + 1; // Calculate wirelength after initial placement diff --git a/dummy/arch_place.cc b/dummy/arch_place.cc index 15f813ae..07ff53ae 100644 --- a/dummy/arch_place.cc +++ b/dummy/arch_place.cc @@ -26,4 +26,9 @@ bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel) return true; } +bool isBelLocationValid(Design *design, BelId bel) +{ + return true; +} + NEXTPNR_NAMESPACE_END diff --git a/dummy/arch_place.h b/dummy/arch_place.h index 66789b7d..1e14ec68 100644 --- a/dummy/arch_place.h +++ b/dummy/arch_place.h @@ -31,6 +31,9 @@ NEXTPNR_NAMESPACE_BEGIN // such as conflicting set/reset signals, etc bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel); +// Return true whether all Bels at a given location are valid +bool isBelLocationValid(Design *design, BelId bel); + NEXTPNR_NAMESPACE_END #endif diff --git a/frontend/json/jsonparse.cc b/frontend/json/jsonparse.cc index 0b06f980..3c060fd7 100644 --- a/frontend/json/jsonparse.cc +++ b/frontend/json/jsonparse.cc @@ -741,9 +741,10 @@ void json_import(Design *design, string modname, JsonNode *node) netnames.resize(netid + 1); netnames.at(netid) = basename + - (num_bits == 1 ? "" : std::string("[") + - std::to_string(i) + - std::string("]")); + (num_bits == 1 + ? "" + : std::string("[") + std::to_string(i) + + std::string("]")); } } } diff --git a/ice40/cells.cc b/ice40/cells.cc index b11a2a77..fb264051 100644 --- a/ice40/cells.cc +++ b/ice40/cells.cc @@ -147,7 +147,8 @@ void dff_to_lc(CellInfo *dff, CellInfo *lc, bool pass_thru_lut) if (citer != config.end()) { if ((config.end() - citer) >= 2) { - assert(*(citer++) == 'S'); + char c = *(citer++); + assert(c == 'S'); lc->params["ASYNC_SR"] = "0"; } else { lc->params["ASYNC_SR"] = "1"; -- cgit v1.2.3 From a965b91321fd22eb2b2e99d17abdeb419a31512d Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 18 Jun 2018 11:45:54 +0200 Subject: Enable -Wall Signed-off-by: David Shah --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index b9c0ff6c..06e83f6e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -4,7 +4,7 @@ project(nextpnr) # List of families to build set(FAMILIES dummy ice40) set(CMAKE_CXX_STANDARD 11) -# set(CMAKE_CXX_FLAGS "-Wall -pedantic -Wextra -Werror") +set(CMAKE_CXX_FLAGS "-Wall") set(CMAKE_DEFIN) # List of Boost libraries to include set(boost_libs filesystem thread program_options) -- cgit v1.2.3 From ef2d0d2cb9e149839b1cba746624becae4d7c5df Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 18 Jun 2018 12:20:06 +0200 Subject: Fix hash specialisation for BelType and warnings in place_sa.cc Signed-off-by: David Shah --- common/place_sa.cc | 24 +++++++++++------------- ice40/chip.h | 11 +++++++++++ 2 files changed, 22 insertions(+), 13 deletions(-) diff --git a/common/place_sa.cc b/common/place_sa.cc index 6012adf8..25297d31 100644 --- a/common/place_sa.cc +++ b/common/place_sa.cc @@ -161,7 +161,6 @@ static float get_wirelength(Chip *chip, NetInfo *net) if (load.cell == nullptr) continue; CellInfo *load_cell = load.cell; - int load_x = 0, load_y = 0; if (load_cell->bel == BelId()) continue; // chip->estimatePosition(load_cell->bel, load_x, load_y); @@ -265,7 +264,6 @@ swap_fail: BelId random_bel_for_cell(Design *design, CellInfo *cell, SAState &state, rnd_state &rnd) { - BelId best_bel = BelId(); Chip &chip = design->chip; BelType targetType = belTypeFromId(cell->type); int x = 0, y = 0; @@ -276,9 +274,9 @@ BelId random_bel_for_cell(Design *design, CellInfo *cell, SAState &state, int ny = random_int_between(rnd, std::max(int(y) - state.diameter, 0), int(y) + state.diameter + 1); int beltype_idx = state.bel_types.at(targetType); - if (nx >= state.fast_bels.at(beltype_idx).size()) + if (nx >= int(state.fast_bels.at(beltype_idx).size())) continue; - if (ny >= state.fast_bels.at(beltype_idx).at(nx).size()) + if (ny >= int(state.fast_bels.at(beltype_idx).at(nx).size())) continue; const auto &fb = state.fast_bels.at(beltype_idx).at(nx).at(ny); if (fb.size() == 0) @@ -294,7 +292,7 @@ void place_design_sa(Design *design, int seed) { SAState state; - size_t total_cells = design->cells.size(), placed_cells = 0; + size_t placed_cells = 0; std::queue visit_cells; // Initial constraints placer for (auto cell_entry : design->cells) { @@ -356,15 +354,15 @@ void place_design_sa(Design *design, int seed) } else { type_idx = state.bel_types.at(type); } - if (state.fast_bels.size() < type_idx + 1) + if (int(state.fast_bels.size()) < type_idx + 1) state.fast_bels.resize(type_idx + 1); - if (state.fast_bels.at(type_idx).size() < int(x) + 1) - state.fast_bels.at(type_idx).resize(int(x) + 1); - if (state.fast_bels.at(type_idx).at(int(x)).size() < int(y) + 1) - state.fast_bels.at(type_idx).at(int(x)).resize(int(y) + 1); - max_x = std::max(max_x, int(x)); - max_y = std::max(max_y, int(y)); - state.fast_bels.at(type_idx).at(int(x)).at(int((y))).push_back(bel); + if (int(state.fast_bels.at(type_idx).size()) < (x + 1)) + state.fast_bels.at(type_idx).resize(x + 1); + if (int(state.fast_bels.at(type_idx).at(x).size()) < (y + 1)) + state.fast_bels.at(type_idx).at(x).resize(y + 1); + max_x = std::max(max_x, x); + max_y = std::max(max_y, y); + state.fast_bels.at(type_idx).at(x).at(y).push_back(bel); } state.diameter = std::max(max_x, max_y) + 1; // Calculate wirelength after initial placement diff --git a/ice40/chip.h b/ice40/chip.h index 9d647756..d3eb7c70 100644 --- a/ice40/chip.h +++ b/ice40/chip.h @@ -743,4 +743,15 @@ struct Chip NEXTPNR_NAMESPACE_END +namespace std { +template <> struct hash +{ + std::size_t operator()(NEXTPNR_NAMESPACE_PREFIX BelType bt) const + noexcept + { + return std::hash()(int(bt)); + } +}; +} // namespace std + #endif -- cgit v1.2.3 From 9a2692039a9f407b264421169d5f33b401a0f907 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 18 Jun 2018 12:22:48 +0200 Subject: cmake: Reenable -O3 for release builds Signed-off-by: David Shah --- CMakeLists.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 06e83f6e..8901d6cc 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -4,7 +4,8 @@ project(nextpnr) # List of families to build set(FAMILIES dummy ice40) set(CMAKE_CXX_STANDARD 11) -set(CMAKE_CXX_FLAGS "-Wall") +set(CMAKE_CXX_FLAGS_DEBUG "-Wall") +set(CMAKE_CXX_FLAGS_RELEASE "-Wall -O3 -g") set(CMAKE_DEFIN) # List of Boost libraries to include set(boost_libs filesystem thread program_options) -- cgit v1.2.3 From bb4c70381338e1a84920cc2d62648910528fee1c Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 18 Jun 2018 13:11:53 +0200 Subject: cmake: Set EXCLUDE_FROM_ALL on Python module and tests Signed-off-by: David Shah --- CMakeLists.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 8901d6cc..8f3c6183 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -94,10 +94,10 @@ foreach (family ${FAMILIES}) target_compile_definitions(nextpnr-${family} PRIVATE MAIN_EXECUTABLE) # Add the importable Python module target - PYTHON_ADD_MODULE(nextpnrpy_${family} ${COMMON_FILES} ${${ufamily}_FILES}) + PYTHON_ADD_MODULE(nextpnrpy_${family} EXCLUDE_FROM_ALL ${COMMON_FILES} ${${ufamily}_FILES}) # Add any new per-architecture targets here - add_executable(nextpnr-${family}-test ${${ufamily}_TEST_FILES} ${COMMON_FILES} ${${ufamily}_FILES}) + add_executable(nextpnr-${family}-test EXCLUDE_FROM_ALL ${${ufamily}_TEST_FILES} ${COMMON_FILES} ${${ufamily}_FILES}) target_link_libraries(nextpnr-${family}-test PRIVATE gtest_main) add_test(${family}-test ${CMAKE_CURRENT_BINARY_DIR}/nextpnr-${family}-test) -- cgit v1.2.3