From 5a7f83c705d6ea52e9e5bb7b182b32040d15a13a Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Tue, 16 Feb 2021 12:24:15 -0800 Subject: Add examples invoking FPGA interchange nextpnr. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- fpga_interchange/examples/archcheck/Makefile | 16 +++++ fpga_interchange/examples/archcheck/test_data.yaml | 7 +++ fpga_interchange/examples/lut/Makefile | 8 +++ fpga_interchange/examples/lut/lut.v | 5 ++ fpga_interchange/examples/lut/lut.xdc | 5 ++ fpga_interchange/examples/lut/run.tcl | 14 +++++ fpga_interchange/examples/template.mk | 68 ++++++++++++++++++++++ fpga_interchange/examples/wire/Makefile | 8 +++ fpga_interchange/examples/wire/run.tcl | 14 +++++ fpga_interchange/examples/wire/wire.v | 5 ++ fpga_interchange/examples/wire/wire.xdc | 2 + 11 files changed, 152 insertions(+) create mode 100644 fpga_interchange/examples/archcheck/Makefile create mode 100644 fpga_interchange/examples/archcheck/test_data.yaml create mode 100644 fpga_interchange/examples/lut/Makefile create mode 100644 fpga_interchange/examples/lut/lut.v create mode 100644 fpga_interchange/examples/lut/lut.xdc create mode 100644 fpga_interchange/examples/lut/run.tcl create mode 100644 fpga_interchange/examples/template.mk create mode 100644 fpga_interchange/examples/wire/Makefile create mode 100644 fpga_interchange/examples/wire/run.tcl create mode 100644 fpga_interchange/examples/wire/wire.v create mode 100644 fpga_interchange/examples/wire/wire.xdc diff --git a/fpga_interchange/examples/archcheck/Makefile b/fpga_interchange/examples/archcheck/Makefile new file mode 100644 index 00000000..8984e1b4 --- /dev/null +++ b/fpga_interchange/examples/archcheck/Makefile @@ -0,0 +1,16 @@ +NEXTPNR_PATH := $(shell echo ~/cat_x/nextpnr) +NEXTPNR_BIN := $(NEXTPNR_PATH)/build/nextpnr-fpga_interchange +BBA_PATH := $(NEXTPNR_PATH)/build/test.bin + +PACKAGE := csg324 + +.PHONY: + +check: + $(NEXTPNR_BIN) \ + --chipdb $(BBA_PATH) \ + --package $(PACKAGE) \ + --test + $(NEXTPNR_BIN) \ + --chipdb $(BBA_PATH) \ + --run $(NEXTPNR_PATH)/python/check_arch_api.py diff --git a/fpga_interchange/examples/archcheck/test_data.yaml b/fpga_interchange/examples/archcheck/test_data.yaml new file mode 100644 index 00000000..b41112cf --- /dev/null +++ b/fpga_interchange/examples/archcheck/test_data.yaml @@ -0,0 +1,7 @@ +pip_test: + - src_wire: CLBLM_R_X11Y93/CLBLM_L_D3 + dst_wire: SLICE_X15Y93.SLICEL/D3 +bel_pin_test: + - bel: SLICE_X15Y93.SLICEL/D6LUT + pin: A3 + wire: SLICE_X15Y93.SLICEL/D3 diff --git a/fpga_interchange/examples/lut/Makefile b/fpga_interchange/examples/lut/Makefile new file mode 100644 index 00000000..54fc8994 --- /dev/null +++ b/fpga_interchange/examples/lut/Makefile @@ -0,0 +1,8 @@ +DESIGN := lut +DESIGN_TOP := top +PACKAGE := csg324 + +include ../template.mk + +build/lut.json: lut.v | build + yosys -c run.tcl diff --git a/fpga_interchange/examples/lut/lut.v b/fpga_interchange/examples/lut/lut.v new file mode 100644 index 00000000..ca18e665 --- /dev/null +++ b/fpga_interchange/examples/lut/lut.v @@ -0,0 +1,5 @@ +module top(input i0, input i1, output o); + +assign o = i0 | i1; + +endmodule diff --git a/fpga_interchange/examples/lut/lut.xdc b/fpga_interchange/examples/lut/lut.xdc new file mode 100644 index 00000000..4f7e948b --- /dev/null +++ b/fpga_interchange/examples/lut/lut.xdc @@ -0,0 +1,5 @@ +set_property PACKAGE_PIN N16 [get_ports i0] +set_property PACKAGE_PIN N15 [get_ports i1] +set_property PACKAGE_PIN M17 [get_ports o] + +#set_property IOSTANDARD LVCMOS33 [get_ports] diff --git a/fpga_interchange/examples/lut/run.tcl b/fpga_interchange/examples/lut/run.tcl new file mode 100644 index 00000000..1edd8bb7 --- /dev/null +++ b/fpga_interchange/examples/lut/run.tcl @@ -0,0 +1,14 @@ +yosys -import + +read_verilog lut.v + +synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json build/lut.json diff --git a/fpga_interchange/examples/template.mk b/fpga_interchange/examples/template.mk new file mode 100644 index 00000000..11710058 --- /dev/null +++ b/fpga_interchange/examples/template.mk @@ -0,0 +1,68 @@ +NEXTPNR_PATH := $(shell echo ~/cat_x/nextpnr) +NEXTPNR_BIN := $(NEXTPNR_PATH)/build/nextpnr-fpga_interchange +BBA_PATH := $(NEXTPNR_PATH)/build/test.bin + +RAPIDWRIGHT_PATH := $(shell echo ~/cat_x/RapidWright) + +INTERCHANGE_PATH := $(NEXTPNR_PATH)/3rdparty/fpga-interchange-schema/interchange + +DEVICE := $(shell echo ~/cat_x/python-fpga-interchange/xc7a35tcpg236-1_constraints_luts.device) + +.DELETE_ON_ERROR: +.PHONY: all debug clean + +all: build/$(DESIGN).dcp + +build: + mkdir build + +build/$(DESIGN).netlist: build/$(DESIGN).json + /usr/bin/time -v python3 -mfpga_interchange.yosys_json \ + --schema_dir $(INTERCHANGE_PATH) \ + --device $(DEVICE) \ + --top $(DESIGN_TOP) \ + build/$(DESIGN).json \ + build/$(DESIGN).netlist + +build/$(DESIGN)_netlist.yaml: build/$(DESIGN).netlist + /usr/bin/time -v python3 -mfpga_interchange.convert \ + --schema_dir $(INTERCHANGE_PATH) \ + --schema logical \ + --input_format capnp \ + --output_format yaml \ + build/$(DESIGN).netlist \ + build/$(DESIGN)_netlist.yaml + +build/$(DESIGN).phys: build/$(DESIGN).netlist + $(NEXTPNR_BIN) \ + --chipdb $(BBA_PATH) \ + --xdc $(DESIGN).xdc \ + --netlist build/$(DESIGN).netlist \ + --phys build/$(DESIGN).phys \ + --package $(PACKAGE) + +build/$(DESIGN)_phys.yaml: build/$(DESIGN).phys + /usr/bin/time -v python3 -mfpga_interchange.convert \ + --schema_dir $(INTERCHANGE_PATH) \ + --schema physical \ + --input_format capnp \ + --output_format yaml \ + build/$(DESIGN).phys \ + build/$(DESIGN)_phys.yaml + +debug: build/$(DESIGN).netlist + gdb --args $(NEXTPNR_BIN) \ + --chipdb $(BBA_PATH) \ + --xdc $(DESIGN).xdc \ + --netlist build/$(DESIGN).netlist \ + --phys build/$(DESIGN).phys \ + --package $(PACKAGE) + +build/$(DESIGN).dcp: build/$(DESIGN).netlist build/$(DESIGN).phys $(DESIGN).xdc + RAPIDWRIGHT_PATH=$(RAPIDWRIGHT_PATH) \ + $(RAPIDWRIGHT_PATH)/scripts/invoke_rapidwright.sh \ + com.xilinx.rapidwright.interchange.PhysicalNetlistToDcp \ + build/$(DESIGN).netlist build/$(DESIGN).phys $(DESIGN).xdc build/$(DESIGN).dcp + +clean:: + rm -rf build diff --git a/fpga_interchange/examples/wire/Makefile b/fpga_interchange/examples/wire/Makefile new file mode 100644 index 00000000..49194f53 --- /dev/null +++ b/fpga_interchange/examples/wire/Makefile @@ -0,0 +1,8 @@ +DESIGN := wire +DESIGN_TOP := top +PACKAGE := csg324 + +include ../template.mk + +build/wire.json: wire.v | build + yosys -c run.tcl diff --git a/fpga_interchange/examples/wire/run.tcl b/fpga_interchange/examples/wire/run.tcl new file mode 100644 index 00000000..9127be20 --- /dev/null +++ b/fpga_interchange/examples/wire/run.tcl @@ -0,0 +1,14 @@ +yosys -import + +read_verilog wire.v + +synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json build/wire.json diff --git a/fpga_interchange/examples/wire/wire.v b/fpga_interchange/examples/wire/wire.v new file mode 100644 index 00000000..429d05ff --- /dev/null +++ b/fpga_interchange/examples/wire/wire.v @@ -0,0 +1,5 @@ +module top(input i, output o); + +assign o = i; + +endmodule diff --git a/fpga_interchange/examples/wire/wire.xdc b/fpga_interchange/examples/wire/wire.xdc new file mode 100644 index 00000000..e1fce5f0 --- /dev/null +++ b/fpga_interchange/examples/wire/wire.xdc @@ -0,0 +1,2 @@ +set_property PACKAGE_PIN N16 [get_ports i] +set_property PACKAGE_PIN N15 [get_ports o] -- cgit v1.2.3