From 6ffae27aa14ee48ebd5713e540bfc53568e56fd6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 11 Jul 2018 18:36:15 +0200 Subject: Deterministic chipdb blobs Signed-off-by: Clifford Wolf --- ecp5/trellis_import.py | 2 +- ice40/chipdb.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py index 60e48844..5fdd7296 100755 --- a/ecp5/trellis_import.py +++ b/ecp5/trellis_import.py @@ -331,7 +331,7 @@ class BinaryBlobAssembler: def finalize(self): assert not self.finalized - for s, index in self.strings.items(): + for s, index in sorted(self.strings.items()): self.l("str%d" % index, "char") for c in s: self.data.append(ord(c)) diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 931c73d1..2a918ed9 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -712,7 +712,7 @@ class BinaryBlobAssembler: def finalize(self): assert not self.finalized - for s, index in self.strings.items(): + for s, index in sorted(self.strings.items()): self.l("str%d" % index, "char") for c in s: self.data.append(ord(c)) @@ -947,7 +947,7 @@ for wire in range(num_wires): if wire in wire_downhill_belports: num_bels_downhill = len(wire_downhill_belports[wire]) bba.l("wire%d_downbels" % wire, "BelPortPOD") - for belport in wire_downhill_belports[wire]: + for belport in sorted(wire_downhill_belports[wire]): bba.u32(belport[0], "bel_index") bba.u32(portpins[belport[1]], "port") else: -- cgit v1.2.3