From 7787ce5fd934b2d794e1fa15b6e8007ed07080e6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 14 Jun 2018 12:43:00 +0200 Subject: Refactor position/delay estimation API Signed-off-by: Clifford Wolf --- common/route.cc | 29 +++++++++++++---------------- dummy/chip.cc | 33 +++++---------------------------- dummy/chip.h | 11 ++--------- ice40/chip.cc | 36 +++++++++++++----------------------- ice40/chip.h | 11 ++--------- ice40/pybindings.cc | 4 ++-- 6 files changed, 37 insertions(+), 87 deletions(-) diff --git a/common/route.cc b/common/route.cc index d175670d..7bb58430 100644 --- a/common/route.cc +++ b/common/route.cc @@ -45,7 +45,7 @@ struct QueuedWire void route_design(Design *design, bool verbose) { auto &chip = design->chip; - int itercnt = 0, netcnt = 0; + int visitCnt = 0, revisitCnt = 0, netCnt = 0; float maxDelay = 0.0; int failedPathCnt = 0; @@ -62,7 +62,7 @@ void route_design(Design *design, bool verbose) if (verbose) log("Routing net %s.\n", net_name.c_str()); - netcnt++; + netCnt++; if (verbose) log(" Source: %s.%s.\n", net_info->driver.cell->name.c_str(), @@ -78,8 +78,6 @@ void route_design(Design *design, bool verbose) if (verbose) log(" Source bel: %s\n", chip.getBelName(src_bel).c_str()); - auto src_pos = chip.getBelPosition(src_bel); - IdString driver_port = net_info->driver.port; auto driver_port_it = net_info->driver.cell->pins.find(driver_port); @@ -109,19 +107,15 @@ void route_design(Design *design, bool verbose) user_it.port.c_str()); auto dst_bel = user_it.cell->bel; - auto dst_pos = chip.getBelPosition(dst_bel); if (dst_bel == BelId()) log_error("Destination cell %s (%s) is not mapped to a bel.\n", user_it.cell->name.c_str(), user_it.cell->type.c_str()); - if (verbose) { + if (verbose) log(" Destination bel: %s\n", chip.getBelName(dst_bel).c_str()); - log(" Path delay estimate: %.2f\n", - chip.estimateDelay(src_pos, dst_pos)); - } IdString user_port = user_it.port; @@ -140,9 +134,12 @@ void route_design(Design *design, bool verbose) user_it.cell->name.c_str(), chip.getBelName(dst_bel).c_str()); - if (verbose) + if (verbose) { log(" Destination wire: %s\n", chip.getWireName(dst_wire).c_str()); + log(" Path delay estimate: %.2f\n", + chip.estimateDelay(src_wire, dst_wire)); + } std::unordered_map visited; std::priority_queue, @@ -154,15 +151,14 @@ void route_design(Design *design, bool verbose) qw.wire = it.first; qw.pip = PipId(); qw.delay = it.second.avgDelay(); - qw.togo = chip.estimateDelay(chip.getWirePosition(qw.wire), - dst_pos); + qw.togo = chip.estimateDelay(qw.wire, dst_wire); queue.push(qw); visited[qw.wire] = qw; } while (!queue.empty()) { - itercnt++; + visitCnt++; QueuedWire qw = queue.top(); queue.pop(); @@ -182,6 +178,7 @@ void route_design(Design *design, bool verbose) "estimate: %.2f %.2f\n", chip.getWireName(next_wire).c_str(), visited.at(next_wire).delay, next_delay); + revisitCnt++; } if (!chip.checkWireAvail(next_wire)) @@ -191,8 +188,7 @@ void route_design(Design *design, bool verbose) next_qw.wire = next_wire; next_qw.pip = pip; next_qw.delay = next_delay; - next_qw.togo = chip.estimateDelay( - chip.getWirePosition(next_wire), dst_pos); + next_qw.togo = chip.estimateDelay(next_wire, dst_wire); visited[next_qw.wire] = next_qw; queue.push(next_qw); @@ -242,7 +238,8 @@ void route_design(Design *design, bool verbose) } } - log_info("routed %d nets, visited %d wires.\n", netcnt, itercnt); + log_info("routed %d nets, visited %d wires (%.2f%% revisits).\n", netCnt, + visitCnt, (100.0 * revisitCnt) / visitCnt); log_info("longest path delay: %.2f\n", maxDelay); if (failedPathCnt > 0) diff --git a/dummy/chip.cc b/dummy/chip.cc index b8a23709..d9543643 100644 --- a/dummy/chip.cc +++ b/dummy/chip.cc @@ -141,37 +141,14 @@ const std::vector &Chip::getWireAliases(WireId wire) const // --------------------------------------------------------------- -PosInfo Chip::getBelPosition(BelId bel) const +bool Chip::estimatePosition(BelId bel, float &x, float &y) const { - PosInfo pos; - assert(bel != BelId()); - // pos.x = ...; - // pos.y = ...; - return pos; + x = 0.0; + y = 0.0; + return false; } -PosInfo Chip::getWirePosition(WireId wire) const -{ - PosInfo pos; - assert(wire != WireId()); - // pos.x = ...; - // pos.y = ...; - return pos; -} - -PosInfo Chip::getPipPosition(PipId pip) const -{ - PosInfo pos; - assert(pip != PipId()); - // pos.x = ...; - // pos.y = ...; - return pos; -} - -float Chip::estimateDelay(PosInfo src, PosInfo dst) const -{ - return fabsf(src.x - dst.x) + fabsf(src.x - dst.x); -} +float Chip::estimateDelay(WireId src, WireId dst) const { return 0.0; } // --------------------------------------------------------------- diff --git a/dummy/chip.h b/dummy/chip.h index 197e84f1..4fd86bdb 100644 --- a/dummy/chip.h +++ b/dummy/chip.h @@ -42,11 +42,6 @@ struct DelayInfo } }; -struct PosInfo -{ - float x = 0, y = 0; -}; - typedef IdString BelType; typedef IdString PortPin; @@ -113,10 +108,8 @@ struct Chip const std::vector &getPipsUphill(WireId wire) const; const std::vector &getWireAliases(WireId wire) const; - PosInfo getBelPosition(BelId bel) const; - PosInfo getWirePosition(WireId wire) const; - PosInfo getPipPosition(PipId pip) const; - float estimateDelay(PosInfo src, PosInfo dst) const; + bool estimatePosition(BelId bel, float &x, float &y) const; + float estimateDelay(WireId src, WireId dst) const; std::vector getFrameGraphics() const; std::vector getBelGraphics(BelId bel) const; diff --git a/ice40/chip.cc b/ice40/chip.cc index 87428339..b40963bf 100644 --- a/ice40/chip.cc +++ b/ice40/chip.cc @@ -275,36 +275,26 @@ BelId Chip::getPackagePinBel(const std::string &pin) const // ----------------------------------------------------------------------- -PosInfo Chip::getBelPosition(BelId bel) const +bool Chip::estimatePosition(BelId bel, float &x, float &y) const { - PosInfo pos; assert(bel != BelId()); - pos.x = chip_info.bel_data[bel.index].x; - pos.y = chip_info.bel_data[bel.index].y; - return pos; -} + x = chip_info.bel_data[bel.index].x; + y = chip_info.bel_data[bel.index].y; -PosInfo Chip::getWirePosition(WireId wire) const -{ - PosInfo pos; - assert(wire != WireId()); - pos.x = chip_info.wire_data[wire.index].x; - pos.y = chip_info.wire_data[wire.index].y; - return pos; + return chip_info.bel_data[bel.index].type != TYPE_SB_GB; } -PosInfo Chip::getPipPosition(PipId pip) const +float Chip::estimateDelay(WireId src, WireId dst) const { - PosInfo pos; - assert(pip != PipId()); - pos.x = chip_info.pip_data[pip.index].x; - pos.y = chip_info.pip_data[pip.index].y; - return pos; -} + assert(src != WireId()); + float x1 = chip_info.wire_data[src.index].x; + float y1 = chip_info.wire_data[src.index].y; -float Chip::estimateDelay(PosInfo src, PosInfo dst) const -{ - return fabsf(src.x - dst.x) + fabsf(src.y - dst.y); + assert(dst != WireId()); + float x2 = chip_info.wire_data[dst.index].x; + float y2 = chip_info.wire_data[dst.index].y; + + return fabsf(x1 - x2) + fabsf(y1 - y2); } // ----------------------------------------------------------------------- diff --git a/ice40/chip.h b/ice40/chip.h index 6700666f..54e8e368 100644 --- a/ice40/chip.h +++ b/ice40/chip.h @@ -42,11 +42,6 @@ struct DelayInfo } }; -struct PosInfo -{ - float x = 0, y = 0; -}; - // ----------------------------------------------------------------------- enum BelType @@ -693,10 +688,8 @@ struct Chip // ------------------------------------------------- - PosInfo getBelPosition(BelId bel) const; - PosInfo getWirePosition(WireId wire) const; - PosInfo getPipPosition(PipId pip) const; - float estimateDelay(PosInfo src, PosInfo dst) const; + bool estimatePosition(BelId bel, float &x, float &y) const; + float estimateDelay(WireId src, WireId dst) const; // ------------------------------------------------- diff --git a/ice40/pybindings.cc b/ice40/pybindings.cc index 9094fe7c..5ccf9495 100644 --- a/ice40/pybindings.cc +++ b/ice40/pybindings.cc @@ -73,8 +73,8 @@ void arch_wrap_python() .def("getPipsDownhill", &Chip::getPipsDownhill) .def("getPipsUphill", &Chip::getPipsUphill) .def("getWireAliases", &Chip::getWireAliases) - .def("getBelPosition", &Chip::getBelPosition) - .def("getWirePosition", &Chip::getWirePosition); + .def("estimatePosition", &Chip::estimatePosition) + .def("estimateDelay", &Chip::estimateDelay); WRAP_RANGE(Bel); WRAP_RANGE(BelPin); -- cgit v1.2.3