From 7cff69f9453e0c95f8eb9a12b004afa20b69501e Mon Sep 17 00:00:00 2001 From: "D. Shah" Date: Tue, 2 Feb 2021 14:48:29 +0000 Subject: generic: Use IdStringList for all arch object names Signed-off-by: D. Shah --- common/nextpnr.h | 15 +++++++++ common/pybindings.h | 12 +++++++ common/timing_opt.cc | 2 +- generic/arch.cc | 74 +++++++++++++++++++++++-------------------- generic/arch.h | 79 ++++++++++++++++++++++++---------------------- generic/arch_pybindings.cc | 62 ++++++++++++++++++------------------ generic/archdefs.h | 10 +++--- 7 files changed, 146 insertions(+), 108 deletions(-) diff --git a/common/nextpnr.h b/common/nextpnr.h index d4db9e9e..78bbf66e 100644 --- a/common/nextpnr.h +++ b/common/nextpnr.h @@ -243,6 +243,21 @@ struct IdStringList const IdString &operator[](size_t idx) const { return ids[idx]; } bool operator==(const IdStringList &other) const { return ids == other.ids; } bool operator!=(const IdStringList &other) const { return ids != other.ids; } + bool operator<(const IdStringList &other) const + { + if (size() > other.size()) + return false; + if (size() < other.size()) + return true; + for (size_t i = 0; i < size(); i++) { + IdString a = ids[i], b = other[i]; + if (a.index < b.index) + return true; + if (a.index > b.index) + return false; + } + return false; + } }; NEXTPNR_NAMESPACE_END diff --git a/common/pybindings.h b/common/pybindings.h index e50ffd1b..3e33a374 100644 --- a/common/pybindings.h +++ b/common/pybindings.h @@ -74,6 +74,18 @@ template <> struct string_converter inline std::string to_str(Context *ctx, IdString id) { return id.str(ctx); } }; +template <> struct string_converter +{ + IdStringList from_str(Context *ctx, std::string name) { return IdStringList::parse(ctx, name); } + std::string to_str(Context *ctx, const IdStringList &id) { return id.str(ctx); } +}; + +template <> struct string_converter +{ + IdStringList from_str(Context *ctx, std::string name) { return IdStringList::parse(ctx, name); } + std::string to_str(Context *ctx, const IdStringList &id) { return id.str(ctx); } +}; + } // namespace PythonConversion NEXTPNR_NAMESPACE_END diff --git a/common/timing_opt.cc b/common/timing_opt.cc index 7ee7b805..9c601e48 100644 --- a/common/timing_opt.cc +++ b/common/timing_opt.cc @@ -59,7 +59,7 @@ template <> struct hash> return seed; } }; -#if !defined(ARCH_GENERIC) && !defined(ARCH_GOWIN) +#if !defined(ARCH_GOWIN) template <> struct hash> { std::size_t diff --git a/generic/arch.cc b/generic/arch.cc index 4bf337bd..9b131959 100644 --- a/generic/arch.cc +++ b/generic/arch.cc @@ -28,31 +28,31 @@ NEXTPNR_NAMESPACE_BEGIN -WireInfo &Arch::wire_info(IdString wire) +WireInfo &Arch::wire_info(IdStringList wire) { auto w = wires.find(wire); if (w == wires.end()) - NPNR_ASSERT_FALSE_STR("no wire named " + wire.str(this)); + NPNR_ASSERT_FALSE_STR("no wire named " + wire.str(getCtx())); return w->second; } -PipInfo &Arch::pip_info(IdString pip) +PipInfo &Arch::pip_info(IdStringList pip) { auto p = pips.find(pip); if (p == pips.end()) - NPNR_ASSERT_FALSE_STR("no pip named " + pip.str(this)); + NPNR_ASSERT_FALSE_STR("no pip named " + pip.str(getCtx())); return p->second; } -BelInfo &Arch::bel_info(IdString bel) +BelInfo &Arch::bel_info(IdStringList bel) { auto b = bels.find(bel); if (b == bels.end()) - NPNR_ASSERT_FALSE_STR("no bel named " + bel.str(this)); + NPNR_ASSERT_FALSE_STR("no bel named " + bel.str(getCtx())); return b->second; } -void Arch::addWire(IdString name, IdString type, int x, int y) +void Arch::addWire(IdStringList name, IdString type, int x, int y) { NPNR_ASSERT(wires.count(name) == 0); WireInfo &wi = wires[name]; @@ -64,7 +64,8 @@ void Arch::addWire(IdString name, IdString type, int x, int y) wire_ids.push_back(name); } -void Arch::addPip(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay, Loc loc) +void Arch::addPip(IdStringList name, IdString type, IdStringList srcWire, IdStringList dstWire, DelayInfo delay, + Loc loc) { NPNR_ASSERT(pips.count(name) == 0); PipInfo &pi = pips[name]; @@ -90,7 +91,7 @@ void Arch::addPip(IdString name, IdString type, IdString srcWire, IdString dstWi tilePipDimZ[loc.x][loc.y] = std::max(tilePipDimZ[loc.x][loc.y], loc.z + 1); } -void Arch::addBel(IdString name, IdString type, Loc loc, bool gb) +void Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb) { NPNR_ASSERT(bels.count(name) == 0); NPNR_ASSERT(bel_by_loc.count(loc) == 0); @@ -124,7 +125,7 @@ void Arch::addBel(IdString name, IdString type, Loc loc, bool gb) tileBelDimZ[loc.x][loc.y] = std::max(tileBelDimZ[loc.x][loc.y], loc.z + 1); } -void Arch::addBelInput(IdString bel, IdString name, IdString wire) +void Arch::addBelInput(IdStringList bel, IdString name, IdStringList wire) { NPNR_ASSERT(bel_info(bel).pins.count(name) == 0); PinInfo &pi = bel_info(bel).pins[name]; @@ -136,7 +137,7 @@ void Arch::addBelInput(IdString bel, IdString name, IdString wire) wire_info(wire).bel_pins.push_back(BelPin{bel, name}); } -void Arch::addBelOutput(IdString bel, IdString name, IdString wire) +void Arch::addBelOutput(IdStringList bel, IdString name, IdStringList wire) { NPNR_ASSERT(bel_info(bel).pins.count(name) == 0); PinInfo &pi = bel_info(bel).pins[name]; @@ -148,7 +149,7 @@ void Arch::addBelOutput(IdString bel, IdString name, IdString wire) wire_info(wire).bel_pins.push_back(BelPin{bel, name}); } -void Arch::addBelInout(IdString bel, IdString name, IdString wire) +void Arch::addBelInout(IdStringList bel, IdString name, IdStringList wire) { NPNR_ASSERT(bel_info(bel).pins.count(name) == 0); PinInfo &pi = bel_info(bel).pins[name]; @@ -160,13 +161,13 @@ void Arch::addBelInout(IdString bel, IdString name, IdString wire) wire_info(wire).bel_pins.push_back(BelPin{bel, name}); } -void Arch::addGroupBel(IdString group, IdString bel) { groups[group].bels.push_back(bel); } +void Arch::addGroupBel(IdStringList group, IdStringList bel) { groups[group].bels.push_back(bel); } -void Arch::addGroupWire(IdString group, IdString wire) { groups[group].wires.push_back(wire); } +void Arch::addGroupWire(IdStringList group, IdStringList wire) { groups[group].wires.push_back(wire); } -void Arch::addGroupPip(IdString group, IdString pip) { groups[group].pips.push_back(pip); } +void Arch::addGroupPip(IdStringList group, IdStringList pip) { groups[group].pips.push_back(pip); } -void Arch::addGroupGroup(IdString group, IdString grp) { groups[group].groups.push_back(grp); } +void Arch::addGroupGroup(IdStringList group, IdStringList grp) { groups[group].groups.push_back(grp); } void Arch::addDecalGraphic(DecalId decal, const GraphicElement &graphic) { @@ -198,11 +199,14 @@ void Arch::setGroupDecal(GroupId group, DecalXY decalxy) refreshUiGroup(group); } -void Arch::setWireAttr(IdString wire, IdString key, const std::string &value) { wire_info(wire).attrs[key] = value; } +void Arch::setWireAttr(IdStringList wire, IdString key, const std::string &value) +{ + wire_info(wire).attrs[key] = value; +} -void Arch::setPipAttr(IdString pip, IdString key, const std::string &value) { pip_info(pip).attrs[key] = value; } +void Arch::setPipAttr(IdStringList pip, IdString key, const std::string &value) { pip_info(pip).attrs[key] = value; } -void Arch::setBelAttr(IdString bel, IdString key, const std::string &value) { bel_info(bel).attrs[key] = value; } +void Arch::setBelAttr(IdStringList bel, IdString key, const std::string &value) { bel_info(bel).attrs[key] = value; } void Arch::setLutK(int K) { args.K = K; } @@ -212,9 +216,12 @@ void Arch::setDelayScaling(double scale, double offset) args.delayOffset = offset; } -void Arch::addCellTimingClock(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_CLOCK_INPUT; } +void Arch::addCellTimingClock(IdStringList cell, IdString port) +{ + cellTiming[cell].portClasses[port] = TMG_CLOCK_INPUT; +} -void Arch::addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayInfo delay) +void Arch::addCellTimingDelay(IdStringList cell, IdString fromPort, IdString toPort, DelayInfo delay) { if (get_or_default(cellTiming[cell].portClasses, fromPort, TMG_IGNORE) == TMG_IGNORE) cellTiming[cell].portClasses[fromPort] = TMG_COMB_INPUT; @@ -223,7 +230,7 @@ void Arch::addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, cellTiming[cell].combDelays[CellDelayKey{fromPort, toPort}] = delay; } -void Arch::addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold) +void Arch::addCellTimingSetupHold(IdStringList cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold) { TimingClockingInfo ci; ci.clock_port = clock; @@ -234,7 +241,7 @@ void Arch::addCellTimingSetupHold(IdString cell, IdString port, IdString clock, cellTiming[cell].portClasses[port] = TMG_REGISTER_INPUT; } -void Arch::addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayInfo clktoq) +void Arch::addCellTimingClockToOut(IdStringList cell, IdString port, IdString clock, DelayInfo clktoq) { TimingClockingInfo ci; ci.clock_port = clock; @@ -256,14 +263,14 @@ void IdString::initialize_arch(const BaseCtx *ctx) {} // --------------------------------------------------------------- -BelId Arch::getBelByName(IdString name) const +BelId Arch::getBelByName(IdStringList name) const { if (bels.count(name)) return name; return BelId(); } -IdString Arch::getBelName(BelId bel) const { return bel; } +IdStringList Arch::getBelName(BelId bel) const { return bel; } Loc Arch::getBelLocation(BelId bel) const { @@ -321,7 +328,7 @@ WireId Arch::getBelPinWire(BelId bel, IdString pin) const { const auto &bdata = bels.at(bel); if (!bdata.pins.count(pin)) - log_error("bel '%s' has no pin '%s'\n", bel.c_str(this), pin.c_str(this)); + log_error("bel '%s' has no pin '%s'\n", getCtx()->nameOfBel(bel), pin.c_str(this)); return bdata.pins.at(pin).wire; } @@ -337,14 +344,14 @@ std::vector Arch::getBelPins(BelId bel) const // --------------------------------------------------------------- -WireId Arch::getWireByName(IdString name) const +WireId Arch::getWireByName(IdStringList name) const { if (wires.count(name)) return name; return WireId(); } -IdString Arch::getWireName(WireId wire) const { return wire; } +IdStringList Arch::getWireName(WireId wire) const { return wire; } IdString Arch::getWireType(WireId wire) const { return wires.at(wire).type; } @@ -391,14 +398,14 @@ const std::vector &Arch::getWires() const { return wire_ids; } // --------------------------------------------------------------- -PipId Arch::getPipByName(IdString name) const +PipId Arch::getPipByName(IdStringList name) const { if (pips.count(name)) return name; return PipId(); } -IdString Arch::getPipName(PipId pip) const { return pip; } +IdStringList Arch::getPipName(PipId pip) const { return pip; } IdString Arch::getPipType(PipId pip) const { return pips.at(pip).type; } @@ -455,9 +462,9 @@ const std::vector &Arch::getPipsUphill(WireId wire) const { return wires. // --------------------------------------------------------------- -GroupId Arch::getGroupByName(IdString name) const { return name; } +GroupId Arch::getGroupByName(IdStringList name) const { return name; } -IdString Arch::getGroupName(GroupId group) const { return group; } +IdStringList Arch::getGroupName(GroupId group) const { return group; } std::vector Arch::getGroups() const { @@ -582,8 +589,7 @@ bool Arch::route() const std::vector &Arch::getDecalGraphics(DecalId decal) const { if (!decal_graphics.count(decal)) { - std::cerr << "No decal named " << decal.str(this) << std::endl; - log_error("No decal named %s!\n", decal.c_str(this)); + std::cerr << "No decal named " << decal.str(getCtx()) << std::endl; } return decal_graphics.at(decal); } diff --git a/generic/arch.h b/generic/arch.h index 3ec9dc5d..205f388a 100644 --- a/generic/arch.h +++ b/generic/arch.h @@ -36,7 +36,8 @@ struct WireInfo; struct PipInfo { - IdString name, type; + IdStringList name; + IdString type; std::map attrs; NetInfo *bound_net; WireId srcWire, dstWire; @@ -47,7 +48,8 @@ struct PipInfo struct WireInfo { - IdString name, type; + IdStringList name; + IdString type; std::map attrs; NetInfo *bound_net; std::vector downhill, uphill; @@ -60,14 +62,15 @@ struct WireInfo struct PinInfo { - IdString name; + IdStringList name; WireId wire; PortType type; }; struct BelInfo { - IdString name, type; + IdStringList name; + IdString type; std::map attrs; CellInfo *bound_cell; std::unordered_map pins; @@ -78,7 +81,7 @@ struct BelInfo struct GroupInfo { - IdString name; + IdStringList name; std::vector bels; std::vector wires; std::vector pips; @@ -117,17 +120,17 @@ struct Arch : BaseCtx { std::string chipName; - std::unordered_map wires; - std::unordered_map pips; - std::unordered_map bels; + std::unordered_map wires; + std::unordered_map pips; + std::unordered_map bels; std::unordered_map groups; // These functions include useful errors if not found - WireInfo &wire_info(IdString wire); - PipInfo &pip_info(IdString wire); - BelInfo &bel_info(IdString wire); + WireInfo &wire_info(IdStringList wire); + PipInfo &pip_info(IdStringList wire); + BelInfo &bel_info(IdStringList wire); - std::vector bel_ids, wire_ids, pip_ids; + std::vector bel_ids, wire_ids, pip_ids; std::unordered_map bel_by_loc; std::vector>> bels_by_tile; @@ -138,20 +141,20 @@ struct Arch : BaseCtx std::vector> tileBelDimZ; std::vector> tilePipDimZ; - std::unordered_map cellTiming; + std::unordered_map cellTiming; - void addWire(IdString name, IdString type, int x, int y); - void addPip(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay, Loc loc); + void addWire(IdStringList name, IdString type, int x, int y); + void addPip(IdStringList name, IdString type, IdStringList srcWire, IdStringList dstWire, DelayInfo delay, Loc loc); - void addBel(IdString name, IdString type, Loc loc, bool gb); - void addBelInput(IdString bel, IdString name, IdString wire); - void addBelOutput(IdString bel, IdString name, IdString wire); - void addBelInout(IdString bel, IdString name, IdString wire); + void addBel(IdStringList name, IdString type, Loc loc, bool gb); + void addBelInput(IdStringList bel, IdString name, IdStringList wire); + void addBelOutput(IdStringList bel, IdString name, IdStringList wire); + void addBelInout(IdStringList bel, IdString name, IdStringList wire); - void addGroupBel(IdString group, IdString bel); - void addGroupWire(IdString group, IdString wire); - void addGroupPip(IdString group, IdString pip); - void addGroupGroup(IdString group, IdString grp); + void addGroupBel(IdStringList group, IdStringList bel); + void addGroupWire(IdStringList group, IdStringList wire); + void addGroupPip(IdStringList group, IdStringList pip); + void addGroupGroup(IdStringList group, IdStringList grp); void addDecalGraphic(DecalId decal, const GraphicElement &graphic); void setWireDecal(WireId wire, DecalXY decalxy); @@ -159,17 +162,17 @@ struct Arch : BaseCtx void setBelDecal(BelId bel, DecalXY decalxy); void setGroupDecal(GroupId group, DecalXY decalxy); - void setWireAttr(IdString wire, IdString key, const std::string &value); - void setPipAttr(IdString pip, IdString key, const std::string &value); - void setBelAttr(IdString bel, IdString key, const std::string &value); + void setWireAttr(IdStringList wire, IdString key, const std::string &value); + void setPipAttr(IdStringList pip, IdString key, const std::string &value); + void setBelAttr(IdStringList bel, IdString key, const std::string &value); void setLutK(int K); void setDelayScaling(double scale, double offset); - void addCellTimingClock(IdString cell, IdString port); - void addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayInfo delay); - void addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold); - void addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayInfo clktoq); + void addCellTimingClock(IdStringList cell, IdString port); + void addCellTimingDelay(IdStringList cell, IdString fromPort, IdString toPort, DelayInfo delay); + void addCellTimingSetupHold(IdStringList cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold); + void addCellTimingClockToOut(IdStringList cell, IdString port, IdString clock, DelayInfo clktoq); // --------------------------------------------------------------- // Common Arch API. Every arch must provide the following methods. @@ -189,8 +192,8 @@ struct Arch : BaseCtx int getTilePipDimZ(int x, int y) const { return tilePipDimZ[x][y]; } char getNameDelimiter() const { return '/'; } - BelId getBelByName(IdString name) const; - IdString getBelName(BelId bel) const; + BelId getBelByName(IdStringList name) const; + IdStringList getBelName(BelId bel) const; Loc getBelLocation(BelId bel) const; BelId getBelByLocation(Loc loc) const; const std::vector &getBelsByTile(int x, int y) const; @@ -208,8 +211,8 @@ struct Arch : BaseCtx PortType getBelPinType(BelId bel, IdString pin) const; std::vector getBelPins(BelId bel) const; - WireId getWireByName(IdString name) const; - IdString getWireName(WireId wire) const; + WireId getWireByName(IdStringList name) const; + IdStringList getWireName(WireId wire) const; IdString getWireType(WireId wire) const; const std::map &getWireAttrs(WireId wire) const; uint32_t getWireChecksum(WireId wire) const; @@ -223,8 +226,8 @@ struct Arch : BaseCtx const std::vector &getWires() const; const std::vector &getWireBelPins(WireId wire) const; - PipId getPipByName(IdString name) const; - IdString getPipName(PipId pip) const; + PipId getPipByName(IdStringList name) const; + IdStringList getPipName(PipId pip) const; IdString getPipType(PipId pip) const; const std::map &getPipAttrs(PipId pip) const; uint32_t getPipChecksum(PipId pip) const; @@ -242,8 +245,8 @@ struct Arch : BaseCtx const std::vector &getPipsDownhill(WireId wire) const; const std::vector &getPipsUphill(WireId wire) const; - GroupId getGroupByName(IdString name) const; - IdString getGroupName(GroupId group) const; + GroupId getGroupByName(IdStringList name) const; + IdStringList getGroupName(GroupId group) const; std::vector getGroups() const; const std::vector &getGroupBels(GroupId group) const; const std::vector &getGroupWires(GroupId group) const; diff --git a/generic/arch_pybindings.cc b/generic/arch_pybindings.cc index 23f2c05c..4fc76c96 100644 --- a/generic/arch_pybindings.cc +++ b/generic/arch_pybindings.cc @@ -35,6 +35,7 @@ template <> struct string_converter std::string to_str(Context *ctx, const IdString &id) { return id.str(ctx); } }; + } // namespace PythonConversion void arch_wrap_python(py::module &m) @@ -152,37 +153,37 @@ void arch_wrap_python(py::module &m) pass_through>::def_wrap(ctx_cls, "addClock"); // Generic arch construction API - fn_wrapper_4a_v, + fn_wrapper_4a_v, conv_from_str, pass_through, pass_through>::def_wrap(ctx_cls, "addWire", "name"_a, "type"_a, "x"_a, "y"_a); - fn_wrapper_6a_v, - conv_from_str, conv_from_str, conv_from_str, pass_through, - pass_through>::def_wrap(ctx_cls, "addPip", "name"_a, "type"_a, "srcWire"_a, "dstWire"_a, - "delay"_a, "loc"_a); + fn_wrapper_6a_v, + conv_from_str, conv_from_str, conv_from_str, + pass_through, pass_through>::def_wrap(ctx_cls, "addPip", "name"_a, "type"_a, + "srcWire"_a, "dstWire"_a, "delay"_a, "loc"_a); - fn_wrapper_4a_v, + fn_wrapper_4a_v, conv_from_str, pass_through, pass_through>::def_wrap(ctx_cls, "addBel", "name"_a, "type"_a, "loc"_a, "gb"_a); - fn_wrapper_3a_v, - conv_from_str, conv_from_str>::def_wrap(ctx_cls, "addBelInput", "bel"_a, - "name"_a, "wire"_a); - fn_wrapper_3a_v, - conv_from_str, conv_from_str>::def_wrap(ctx_cls, "addBelOutput", "bel"_a, - "name"_a, "wire"_a); - fn_wrapper_3a_v, - conv_from_str, conv_from_str>::def_wrap(ctx_cls, "addBelInout", "bel"_a, - "name"_a, "wire"_a); - - fn_wrapper_2a_v, - conv_from_str>::def_wrap(ctx_cls, "addGroupBel", "group"_a, "bel"_a); - fn_wrapper_2a_v, - conv_from_str>::def_wrap(ctx_cls, "addGroupWire", "group"_a, "wire"_a); - fn_wrapper_2a_v, - conv_from_str>::def_wrap(ctx_cls, "addGroupPip", "group"_a, "pip"_a); - fn_wrapper_2a_v, - conv_from_str>::def_wrap(ctx_cls, "addGroupGroup", "group"_a, "grp"_a); + fn_wrapper_3a_v, + conv_from_str, conv_from_str>::def_wrap(ctx_cls, "addBelInput", "bel"_a, + "name"_a, "wire"_a); + fn_wrapper_3a_v, + conv_from_str, conv_from_str>::def_wrap(ctx_cls, "addBelOutput", "bel"_a, + "name"_a, "wire"_a); + fn_wrapper_3a_v, + conv_from_str, conv_from_str>::def_wrap(ctx_cls, "addBelInout", "bel"_a, + "name"_a, "wire"_a); + + fn_wrapper_2a_v, + conv_from_str>::def_wrap(ctx_cls, "addGroupBel", "group"_a, "bel"_a); + fn_wrapper_2a_v, + conv_from_str>::def_wrap(ctx_cls, "addGroupWire", "group"_a, "wire"_a); + fn_wrapper_2a_v, + conv_from_str>::def_wrap(ctx_cls, "addGroupPip", "group"_a, "pip"_a); + fn_wrapper_2a_v, + conv_from_str>::def_wrap(ctx_cls, "addGroupGroup", "group"_a, "grp"_a); fn_wrapper_2a_v, pass_through>::def_wrap(ctx_cls, "addDecalGraphic", (py::arg("decal"), "graphic")); @@ -211,16 +212,17 @@ void arch_wrap_python(py::module &m) pass_through>::def_wrap(ctx_cls, "setDelayScaling", "scale"_a, "offset"_a); fn_wrapper_2a_v, conv_from_str>::def_wrap(ctx_cls, "addCellTimingClock", "cell"_a, - "port"_a); + conv_from_str, conv_from_str>::def_wrap(ctx_cls, "addCellTimingClock", + "cell"_a, "port"_a); fn_wrapper_4a_v, conv_from_str, conv_from_str, + conv_from_str, conv_from_str, conv_from_str, pass_through>::def_wrap(ctx_cls, "addCellTimingDelay", "cell"_a, "fromPort"_a, "toPort"_a, "delay"_a); fn_wrapper_5a_v, conv_from_str, conv_from_str, pass_through, - pass_through>::def_wrap(ctx_cls, "addCellTimingSetupHold", "cell"_a, "port"_a, "clock"_a, - "setup"_a, "hold"_a); + conv_from_str, conv_from_str, conv_from_str, + pass_through, pass_through>::def_wrap(ctx_cls, "addCellTimingSetupHold", + "cell"_a, "port"_a, "clock"_a, + "setup"_a, "hold"_a); fn_wrapper_4a_v, conv_from_str, conv_from_str, pass_through>::def_wrap(ctx_cls, "addCellTimingClockToOut", "cell"_a, "port"_a, diff --git a/generic/archdefs.h b/generic/archdefs.h index 7623bf40..fad36894 100644 --- a/generic/archdefs.h +++ b/generic/archdefs.h @@ -46,11 +46,11 @@ struct DelayInfo } }; -typedef IdString BelId; -typedef IdString WireId; -typedef IdString PipId; -typedef IdString GroupId; -typedef IdString DecalId; +typedef IdStringList BelId; +typedef IdStringList WireId; +typedef IdStringList PipId; +typedef IdStringList GroupId; +typedef IdStringList DecalId; typedef IdString BelBucketId; struct ArchNetInfo -- cgit v1.2.3