From ad5f6fccaa4484eb02d3fa6d420ff39517b524e6 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 17 Mar 2023 18:58:04 +0100 Subject: Use RelSlice, make more in line with ecp5 arch --- machxo2/arch.cc | 76 ++++++++++++---------------- machxo2/arch.h | 129 +++++++++++++++++++++-------------------------- machxo2/bitstream.cc | 12 ++--- machxo2/facade_import.py | 42 ++++++--------- 4 files changed, 113 insertions(+), 146 deletions(-) diff --git a/machxo2/arch.cc b/machxo2/arch.cc index 82dd51fd..639f6c6b 100644 --- a/machxo2/arch.cc +++ b/machxo2/arch.cc @@ -66,9 +66,9 @@ static void get_chip_info(std::string device, const ChipInfoPOD **chip_info, con *package_info = nullptr; *package_name = pkg.name.get(); *device_name = chip.name.get(); - for (int i = 0; i < (*chip_info)->num_packages; i++) { - if (pkg.name.get() == (*chip_info)->package_info[i].name.get()) { - *package_info = &((*chip_info)->package_info[i]); + for (auto &pi : db_ptr->get()->package_info) { + if (pkg.name.get() == pi.name.get()) { + *package_info = π break; } } @@ -155,7 +155,7 @@ BelId Arch::getBelByName(IdStringList name) const loc.y = id_to_y.at(name[1]); ret.location = loc; const TileTypePOD *loci = tile_info(ret); - for (int i = 0; i < loci->num_bels; i++) { + for (int i = 0; i < loci->bel_data.ssize(); i++) { if (std::strcmp(loci->bel_data[i].name.get(), name[2].c_str(this)) == 0) { ret.index = i; return ret; @@ -174,9 +174,9 @@ BelId Arch::getBelByLocation(Loc loc) const ret.location.x = loc.x; ret.location.y = loc.y; - const TileTypePOD *tilei = tile_info(ret); - for (int i = 0; i < tilei->num_bels; i++) { - if (tilei->bel_data[i].z == loc.z) { + const TileTypePOD *loci = tile_info(ret); + for (int i = 0; i < loci->bel_data.ssize(); i++) { + if (loci->bel_data[i].z == loc.z) { ret.index = i; return ret; } @@ -192,7 +192,7 @@ BelRange Arch::getBelsByTile(int x, int y) const br.b.cursor_tile = y * chip_info->width + x; br.e.cursor_tile = y * chip_info->width + x; br.b.cursor_index = 0; - br.e.cursor_index = chip_info->tiles[y * chip_info->width + x].num_bels - 1; + br.e.cursor_index = chip_info->tiles[y * chip_info->width + x].bel_data.ssize() - 1; br.b.chip = chip_info; br.e.chip = chip_info; if (br.e.cursor_index == -1) @@ -208,16 +208,13 @@ WireId Arch::getBelPinWire(BelId bel, IdString pin) const { NPNR_ASSERT(bel != BelId()); - int num_bel_wires = tile_info(bel)->bel_data[bel.index].num_bel_wires; - const BelWirePOD *bel_wires = &*tile_info(bel)->bel_data[bel.index].bel_wires; - - for (int i = 0; i < num_bel_wires; i++) - if (bel_wires[i].port == pin.index) { + for (auto &bw : tile_info(bel)->bel_data[bel.index].bel_wires) + if (bw.port == pin.index) { WireId ret; - ret.location.x = bel_wires[i].rel_wire_loc.x; - ret.location.y = bel_wires[i].rel_wire_loc.y; - ret.index = bel_wires[i].wire_index; + ret.location.x = bw.rel_wire_loc.x; + ret.location.y = bw.rel_wire_loc.y; + ret.index = bw.wire_index; return ret; } @@ -229,12 +226,9 @@ PortType Arch::getBelPinType(BelId bel, IdString pin) const { NPNR_ASSERT(bel != BelId()); - int num_bel_wires = tile_info(bel)->bel_data[bel.index].num_bel_wires; - const BelWirePOD *bel_wires = &*tile_info(bel)->bel_data[bel.index].bel_wires; - - for (int i = 0; i < num_bel_wires; i++) - if (bel_wires[i].port == pin.index) - return PortType(bel_wires[i].dir); + for (auto &bw : tile_info(bel)->bel_data[bel.index].bel_wires) + if (bw.port == pin.index) + return PortType(bw.type); return PORT_INOUT; } @@ -244,11 +238,9 @@ std::vector Arch::getBelPins(BelId bel) const std::vector ret; NPNR_ASSERT(bel != BelId()); - int num_bel_wires = tile_info(bel)->bel_data[bel.index].num_bel_wires; - const BelWirePOD *bel_wires = &*tile_info(bel)->bel_data[bel.index].bel_wires; - - for (int i = 0; i < num_bel_wires; i++) { - IdString id(bel_wires[i].port); + for (auto &bw : tile_info(bel)->bel_data[bel.index].bel_wires) { + IdString id; + id.index = bw.port; ret.push_back(id); } @@ -259,11 +251,11 @@ std::vector Arch::getBelPins(BelId bel) const BelId Arch::getPackagePinBel(const std::string &pin) const { - for (int i = 0; i < package_info->num_pins; i++) { - if (package_info->pin_data[i].name.get() == pin) { + for (auto &ppin : package_info->pin_data) { + if (ppin.name.get() == pin) { BelId bel; - bel.location = package_info->pin_data[i].abs_loc; - bel.index = package_info->pin_data[i].bel_index; + bel.location = ppin.abs_loc; + bel.index = ppin.bel_index; return bel; } } @@ -282,7 +274,7 @@ WireId Arch::getWireByName(IdStringList name) const loc.y = id_to_y.at(name[1]); ret.location = loc; const TileTypePOD *loci = tile_info(ret); - for (int i = 0; i < loci->num_wires; i++) { + for (int i = 0; i < loci->wire_data.ssize(); i++) { if (std::strcmp(loci->wire_data[i].name.get(), name[2].c_str(this)) == 0) { ret.index = i; return ret; @@ -308,7 +300,7 @@ PipId Arch::getPipByName(IdStringList name) const loc.y = id_to_y.at(name[1]); ret.location = loc; const TileTypePOD *loci = tile_info(ret); - for (int i = 0; i < loci->num_pips; i++) { + for (int i = 0; i < loci->pip_data.ssize(); i++) { PipId curr; curr.location = loc; curr.index = i; @@ -321,13 +313,11 @@ PipId Arch::getPipByName(IdStringList name) const IdStringList Arch::getPipName(PipId pip) const { - auto &pip_data = tile_info(pip)->pips_data[pip.index]; + auto &pip_data = tile_info(pip)->pip_data[pip.index]; WireId src = getPipSrcWire(pip), dst = getPipDstWire(pip); - const char *src_name = tile_info(src)->wire_data[src.index].name.get(); - const char *dst_name = tile_info(dst)->wire_data[dst.index].name.get(); - std::string pip_name = - stringf("%d_%d_%s->%d_%d_%s", pip_data.src.x - pip.location.x, pip_data.src.y - pip.location.y, src_name, - pip_data.dst.x - pip.location.x, pip_data.dst.y - pip.location.y, dst_name); + std::string pip_name = stringf("%d_%d_%s->%d_%d_%s", pip_data.src.x, pip_data.src.y, + get_wire_basename(src).c_str(this), pip_data.dst.x, pip_data.dst.y, + get_wire_basename(dst).c_str(this)); std::array ids{x_ids.at(pip.location.x), y_ids.at(pip.location.y), id(pip_name)}; return IdStringList(ids); @@ -495,13 +485,13 @@ const std::vector Arch::availableRouters = {"router1", "router2"}; bool Arch::cells_compatible(const CellInfo **cells, int count) const { return false; } -std::vector> Arch::get_tiles_at_location(int row, int col) +std::vector> Arch::get_tiles_at_loc(int row, int col) { std::vector> ret; auto &tileloc = chip_info->tile_info[row * chip_info->width + col]; - for (int i = 0; i < tileloc.num_tiles; i++) { - ret.push_back(std::make_pair(tileloc.tile_names[i].name.get(), - chip_info->tiletype_names[tileloc.tile_names[i].type_idx].get())); + for (auto &tn : tileloc.tile_names) { + ret.push_back(std::make_pair(tn.name.get(), + chip_info->tiletype_names[tn.type_idx].get())); } return ret; } diff --git a/machxo2/arch.h b/machxo2/arch.h index efb5ee41..8cb8accc 100644 --- a/machxo2/arch.h +++ b/machxo2/arch.h @@ -39,20 +39,14 @@ NPNR_PACKED_STRUCT(struct BelWirePOD { LocationPOD rel_wire_loc; int32_t wire_index; int32_t port; - int32_t dir; // FIXME: Corresponds to "type" in ECP5. + int32_t type; }); NPNR_PACKED_STRUCT(struct BelInfoPOD { RelPtr name; int32_t type; int32_t z; - int32_t num_bel_wires; - RelPtr bel_wires; -}); - -NPNR_PACKED_STRUCT(struct PipLocatorPOD { - LocationPOD rel_loc; - int32_t index; + RelSlice bel_wires; }); NPNR_PACKED_STRUCT(struct BelPortPOD { @@ -62,35 +56,39 @@ NPNR_PACKED_STRUCT(struct BelPortPOD { }); NPNR_PACKED_STRUCT(struct PipInfoPOD { - LocationPOD src; - LocationPOD dst; - int32_t src_idx; - int32_t dst_idx; + LocationPOD src, dst; + int32_t src_idx, dst_idx; int32_t timing_class; int16_t tile_type; int8_t pip_type; int8_t padding; }); +NPNR_PACKED_STRUCT(struct PipLocatorPOD { + LocationPOD rel_loc; + int32_t index; +}); + NPNR_PACKED_STRUCT(struct WireInfoPOD { RelPtr name; int16_t type; int16_t tile_wire; - int32_t num_uphill; - int32_t num_downhill; - RelPtr pips_uphill; - RelPtr pips_downhill; - int32_t num_bel_pins; - RelPtr bel_pins; + RelSlice pips_uphill, pips_downhill; + RelSlice bel_pins; }); NPNR_PACKED_STRUCT(struct TileTypePOD { - int32_t num_bels; - int32_t num_wires; - int32_t num_pips; - RelPtr bel_data; - RelPtr wire_data; - RelPtr pips_data; + RelSlice bel_data; + RelSlice wire_data; + RelSlice pip_data; +}); + +NPNR_PACKED_STRUCT(struct PIOInfoPOD { + LocationPOD abs_loc; + int32_t bel_index; + RelPtr function_name; + int16_t bank; + int16_t dqsgroup; }); NPNR_PACKED_STRUCT(struct PackagePinPOD { @@ -101,16 +99,7 @@ NPNR_PACKED_STRUCT(struct PackagePinPOD { NPNR_PACKED_STRUCT(struct PackageInfoPOD { RelPtr name; - int32_t num_pins; - RelPtr pin_data; -}); - -NPNR_PACKED_STRUCT(struct PIOInfoPOD { - LocationPOD abs_loc; - int32_t bel_index; - RelPtr function_name; - int16_t bank; - int16_t dqsgroup; + RelSlice pin_data; }); NPNR_PACKED_STRUCT(struct TileNamePOD { @@ -119,10 +108,7 @@ NPNR_PACKED_STRUCT(struct TileNamePOD { int16_t padding; }); -NPNR_PACKED_STRUCT(struct TileInfoPOD { - int32_t num_tiles; - RelPtr tile_names; -}); +NPNR_PACKED_STRUCT(struct TileInfoPOD { RelSlice tile_names; }); NPNR_PACKED_STRUCT(struct PackageSupportedPOD { RelPtr name; @@ -145,13 +131,12 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD { RelPtr device_name; int32_t width, height; int32_t num_tiles; - int32_t num_packages, num_pios; int32_t const_id_count; - RelPtr tiles; - RelPtr> tiletype_names; - RelPtr package_info; - RelPtr pio_info; - RelPtr tile_info; + RelSlice tiles; + RelSlice> tiletype_names; + RelSlice package_info; + RelSlice pio_info; + RelSlice tile_info; RelSlice variants; }); @@ -168,7 +153,7 @@ struct BelIterator BelIterator operator++() { cursor_index++; - while (cursor_tile < chip->num_tiles && cursor_index >= chip->tiles[cursor_tile].num_bels) { + while (cursor_tile < chip->num_tiles && cursor_index >= chip->tiles[cursor_tile].bel_data.ssize()) { cursor_index = 0; cursor_tile++; } @@ -243,7 +228,7 @@ struct WireIterator WireIterator operator++() { cursor_index++; - while (cursor_tile < chip->num_tiles && cursor_index >= chip->tiles[cursor_tile].num_wires) { + while (cursor_tile < chip->num_tiles && cursor_index >= chip->tiles[cursor_tile].wire_data.ssize()) { cursor_index = 0; cursor_tile++; } @@ -293,7 +278,7 @@ struct AllPipIterator AllPipIterator operator++() { cursor_index++; - while (cursor_tile < chip->num_tiles && cursor_index >= chip->tiles[cursor_tile].num_pips) { + while (cursor_tile < chip->num_tiles && cursor_index >= chip->tiles[cursor_tile].pip_data.ssize()) { cursor_index = 0; cursor_tile++; } @@ -518,13 +503,15 @@ struct Arch : BaseArch { BelPinRange range; NPNR_ASSERT(wire != WireId()); - range.b.ptr = tile_info(wire)->wire_data[wire.index].bel_pins.get(); + range.b.ptr = tile_info(wire)->wire_data[wire.index].bel_pins.begin(); range.b.wire_loc = wire.location; - range.e.ptr = range.b.ptr + tile_info(wire)->wire_data[wire.index].num_bel_pins; + range.e.ptr = tile_info(wire)->wire_data[wire.index].bel_pins.end(); range.e.wire_loc = wire.location; return range; } + IdString get_wire_basename(WireId wire) const { return id(tile_info(wire)->wire_data[wire.index].name.get()); } + // Pips PipId getPipByName(IdStringList name) const override; IdStringList getPipName(PipId pip) const override; @@ -558,8 +545,8 @@ struct Arch : BaseArch { WireId wire; NPNR_ASSERT(pip != PipId()); - wire.index = tile_info(pip)->pips_data[pip.index].src_idx; - wire.location = tile_info(pip)->pips_data[pip.index].src; + wire.index = tile_info(pip)->pip_data[pip.index].src_idx; + wire.location = tile_info(pip)->pip_data[pip.index].src; return wire; } @@ -567,8 +554,8 @@ struct Arch : BaseArch { WireId wire; NPNR_ASSERT(pip != PipId()); - wire.index = tile_info(pip)->pips_data[pip.index].dst_idx; - wire.location = tile_info(pip)->pips_data[pip.index].dst; + wire.index = tile_info(pip)->pip_data[pip.index].dst_idx; + wire.location = tile_info(pip)->pip_data[pip.index].dst; return wire; } @@ -580,7 +567,7 @@ struct Arch : BaseArch NPNR_ASSERT(wire != WireId()); range.b.cursor = tile_info(wire)->wire_data[wire.index].pips_downhill.get(); range.b.wire_loc = wire.location; - range.e.cursor = range.b.cursor + tile_info(wire)->wire_data[wire.index].num_downhill; + range.e.cursor = range.b.cursor + tile_info(wire)->wire_data[wire.index].pips_downhill.size(); range.e.wire_loc = wire.location; return range; } @@ -591,20 +578,20 @@ struct Arch : BaseArch NPNR_ASSERT(wire != WireId()); range.b.cursor = tile_info(wire)->wire_data[wire.index].pips_uphill.get(); range.b.wire_loc = wire.location; - range.e.cursor = range.b.cursor + tile_info(wire)->wire_data[wire.index].num_uphill; + range.e.cursor = range.b.cursor + tile_info(wire)->wire_data[wire.index].pips_uphill.size(); range.e.wire_loc = wire.location; return range; } // Extra Pip helpers. - int8_t get_pip_class(PipId pip) const { return tile_info(pip)->pips_data[pip.index].pip_type; } + int8_t get_pip_class(PipId pip) const { return tile_info(pip)->pip_data[pip.index].pip_type; } std::string get_pip_tilename(PipId pip) const { auto &tileloc = chip_info->tile_info[pip.location.y * chip_info->width + pip.location.x]; - for (int i = 0; i < tileloc.num_tiles; i++) { - if (tileloc.tile_names[i].type_idx == tile_info(pip)->pips_data[pip.index].tile_type) - return tileloc.tile_names[i].name.get(); + for (auto &tn : tileloc.tile_names) { + if (tn.type_idx == tile_info(pip)->pip_data[pip.index].tile_type) + return tn.name.get(); } NPNR_ASSERT_FALSE("failed to find Pip tile"); } @@ -646,24 +633,24 @@ struct Arch : BaseArch // Internal usage bool cells_compatible(const CellInfo **cells, int count) const; - std::vector> get_tiles_at_location(int row, int col); - std::string get_tile_by_type_and_loc(int row, int col, std::string type) const + std::vector> get_tiles_at_loc(int row, int col); + std::string get_tile_by_type_loc(int row, int col, std::string type) const { auto &tileloc = chip_info->tile_info[row * chip_info->width + col]; - for (int i = 0; i < tileloc.num_tiles; i++) { - if (chip_info->tiletype_names[tileloc.tile_names[i].type_idx].get() == type) - return tileloc.tile_names[i].name.get(); + for (auto &tn : tileloc.tile_names) { + if (chip_info->tiletype_names[tn.type_idx].get() == type) + return tn.name.get(); } NPNR_ASSERT_FALSE_STR("no tile at (" + std::to_string(col) + ", " + std::to_string(row) + ") with type " + type); } - std::string get_tile_by_type_and_loc(int row, int col, const std::set &type) const + std::string get_tile_by_type_loc(int row, int col, const std::set &type) const { auto &tileloc = chip_info->tile_info[row * chip_info->width + col]; - for (int i = 0; i < tileloc.num_tiles; i++) { - if (type.count(chip_info->tiletype_names[tileloc.tile_names[i].type_idx].get())) - return tileloc.tile_names[i].name.get(); + for (auto &tn : tileloc.tile_names) { + if (type.count(chip_info->tiletype_names[tn.type_idx].get())) + return tn.name.get(); } NPNR_ASSERT_FALSE_STR("no tile at (" + std::to_string(col) + ", " + std::to_string(row) + ") with type in set"); } @@ -672,9 +659,9 @@ struct Arch : BaseArch { for (int i = 0; i < chip_info->height * chip_info->width; i++) { auto &tileloc = chip_info->tile_info[i]; - for (int j = 0; j < tileloc.num_tiles; j++) - if (chip_info->tiletype_names[tileloc.tile_names[j].type_idx].get() == type) - return tileloc.tile_names[j].name.get(); + for (auto &tn : tileloc.tile_names) + if (chip_info->tiletype_names[tn.type_idx].get() == type) + return tn.name.get(); } NPNR_ASSERT_FALSE_STR("no tile with type " + type); } diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc index 232598f3..8cfc408d 100644 --- a/machxo2/bitstream.cc +++ b/machxo2/bitstream.cc @@ -132,7 +132,7 @@ static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire) static void set_pip(Context *ctx, ChipConfig &cc, PipId pip) { std::string tile = ctx->get_pip_tilename(pip); - std::string tile_type = ctx->chip_info->tiletype_names[ctx->tile_info(pip)->pips_data[pip.index].tile_type].get(); + std::string tile_type = ctx->chip_info->tiletype_names[ctx->tile_info(pip)->pip_data[pip.index].tile_type].get(); std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip)); std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip)); cc.tiles[tile].add_arc(sink, source); @@ -179,13 +179,13 @@ static std::string get_pic_tile(Context *ctx, BelId bel) std::string pio_name = ctx->tile_info(bel)->bel_data[bel.index].name.get(); if (bel.location.y == 0) { - return ctx->get_tile_by_type_and_loc(0, bel.location.x, "PIC_T0"); + return ctx->get_tile_by_type_loc(0, bel.location.x, "PIC_T0"); } else if (bel.location.y == ctx->chip_info->height - 1) { - return ctx->get_tile_by_type_and_loc(bel.location.y, bel.location.x, "PIC_B0"); + return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PIC_B0"); } else if (bel.location.x == 0) { - return ctx->get_tile_by_type_and_loc(bel.location.y, 0, pio_l); + return ctx->get_tile_by_type_loc(bel.location.y, 0, pio_l); } else if (bel.location.x == ctx->chip_info->width - 1) { - return ctx->get_tile_by_type_and_loc(bel.location.y, bel.location.x, pio_r); + return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, pio_r); } else { NPNR_ASSERT_FALSE("bad PIO location"); } @@ -226,7 +226,7 @@ void write_bitstream(Context *ctx, std::string text_config_file) } BelId bel = ci->bel; if (ci->type == id_FACADE_SLICE) { - std::string tname = ctx->get_tile_by_type_and_loc(bel.location.y, bel.location.x, "PLC"); + std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC"); std::string slice = ctx->tile_info(bel)->bel_data[bel.index].name.get(); NPNR_ASSERT(slice.substr(0, 5) == "SLICE"); diff --git a/machxo2/facade_import.py b/machxo2/facade_import.py index b83f547d..327d3418 100644 --- a/machxo2/facade_import.py +++ b/machxo2/facade_import.py @@ -308,12 +308,9 @@ def write_database(dev_name, chip, rg, endianness): bba.u16(gfx_wire_ids["TILE_WIRE_" + rg.to_str(wire.name)], "tile_wire") else: bba.u16(0, "tile_wire") - bba.u32(len(wire.arcsUphill), "num_uphill") - bba.u32(len(wire.arcsDownhill), "num_downhill") - bba.r("loc%d_%d_wire%d_uppips" % (l.y, l.x, wire_idx) if len(wire.arcsUphill) > 0 else None, "pips_uphill") - bba.r("loc%d_%d_wire%d_downpips" % (l.y, l.x, wire_idx) if len(wire.arcsDownhill) > 0 else None, "pips_downhill") - bba.u32(len(wire.belPins), "num_bel_pins") - bba.r("loc%d_%d_wire%d_belpins" % (l.y, l.x, wire_idx) if len(wire.belPins) > 0 else None, "bel_pins") + bba.r_slice("loc%d_%d_wire%d_uppips" % (l.y, l.x, wire_idx) if len(wire.arcsUphill) > 0 else None, len(wire.arcsUphill), "pips_uphill") + bba.r_slice("loc%d_%d_wire%d_downpips" % (l.y, l.x, wire_idx) if len(wire.arcsDownhill) > 0 else None, len(wire.arcsDownhill), "pips_downhill") + bba.r_slice("loc%d_%d_wire%d_belpins" % (l.y, l.x, wire_idx) if len(wire.belPins) > 0 else None, len(wire.belPins), "bel_pins") if len(t.bels) > 0: for bel_idx in range(len(t.bels)): @@ -323,15 +320,14 @@ def write_database(dev_name, chip, rg, endianness): write_loc(pin.wire.rel, "rel_wire_loc") bba.u32(pin.wire.id, "wire_index") bba.u32(constids[rg.to_str(pin.pin)], "port") - bba.u32(int(pin.dir), "dir") + bba.u32(int(pin.dir), "type") bba.l("loc%d_%d_bels" % (l.y, l.x), "BelInfoPOD") for bel_idx in range(len(t.bels)): bel = t.bels[bel_idx] bba.s(rg.to_str(bel.name), "name") bba.u32(constids[rg.to_str(bel.type)], "type") bba.u32(bel.z, "z") - bba.u32(len(bel.wires), "num_bel_wires") - bba.r("loc%d_%d_bel%d_wires" % (l.y, l.x, bel_idx), "bel_wires") + bba.r_slice("loc%d_%d_bel%d_wires" % (l.y, l.x, bel_idx), len(bel.wires), "bel_wires") bba.l("tiles", "TileTypePOD") for l in loc_iter: @@ -340,12 +336,9 @@ def write_database(dev_name, chip, rg, endianness): if (l.y, l.x) == (-2, -2): continue - bba.u32(len(t.bels), "num_bels") - bba.u32(len(t.wires), "num_wires") - bba.u32(len(t.arcs), "num_pips") - bba.r("loc%d_%d_bels" % (l.y, l.x) if len(t.bels) > 0 else None, "bel_data") - bba.r("loc%d_%d_wires" % (l.y, l.x) if len(t.wires) > 0 else None, "wire_data") - bba.r("loc%d_%d_pips" % (l.y, l.x) if len(t.arcs) > 0 else None, "pips_data") + bba.r_slice("loc%d_%d_bels" % (l.y, l.x) if len(t.bels) > 0 else None, len(t.bels), "bel_data") + bba.r_slice("loc%d_%d_wires" % (l.y, l.x) if len(t.wires) > 0 else None, len(t.wires), "wire_data") + bba.r_slice("loc%d_%d_pips" % (l.y, l.x) if len(t.arcs) > 0 else None, len(t.arcs), "pips_data") for y in range(0, max_row+1): for x in range(0, max_col+1): @@ -358,8 +351,7 @@ def write_database(dev_name, chip, rg, endianness): bba.l("tiles_info", "TileInfoPOD") for y in range(0, max_row+1): for x in range(0, max_col+1): - bba.u32(len(chip.get_tiles_by_position(y, x)), "num_tiles") - bba.r("tile_info_%d_%d" % (x, y), "tile_names") + bba.r_slice("tile_info_%d_%d" % (x, y), len(chip.get_tiles_by_position(y, x)), "tile_names") for package, pkgdata in sorted(packages.items()): bba.l("package_data_%s" % package, "PackagePinPOD") @@ -372,8 +364,7 @@ def write_database(dev_name, chip, rg, endianness): bba.l("package_data", "PackageInfoPOD") for package, pkgdata in sorted(packages.items()): bba.s(package, "name") - bba.u32(len(pkgdata), "num_pins") - bba.r("package_data_%s" % package, "pin_data") + bba.r_slice("package_data_%s" % package, len(pkgdata), "pin_data") bba.l("pio_info", "PIOInfoPOD") for pin in pindata: @@ -417,18 +408,17 @@ def write_database(dev_name, chip, rg, endianness): bba.u32(max_col + 1, "width") bba.u32(max_row + 1, "height") bba.u32((max_col + 1) * (max_row + 1), "num_tiles") - bba.u32(len(packages), "num_packages") - bba.u32(len(pindata), "num_pios") bba.u32(const_id_count, "const_id_count") - bba.r("tiles", "tiles") - bba.r("tiletype_names", "tiletype_names") - bba.r("package_data", "package_info") - bba.r("pio_info", "pio_info") - bba.r("tiles_info", "tile_info") + bba.r_slice("tiles", (max_col + 1) * (max_row + 1), "tiles") + bba.r_slice("tiletype_names", len(tiletype_names), "tiletype_names") + bba.r_slice("package_data", len(packages), "package_info") + bba.r_slice("pio_info", len(pindata), "pio_info") + bba.r_slice("tiles_info", (max_col + 1) * (max_row + 1), "tile_info") bba.r_slice("variant_data", len(variants), "variant_info") bba.pop() + return bba dev_family = { -- cgit v1.2.3