From e0a851976f7bc51702bc6ba667f36749cd554ebb Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 4 Jul 2018 12:15:23 +0200 Subject: refactor: Replace assert with NPNR_ASSERT Signed-off-by: David Shah --- common/design_utils.cc | 4 +- common/nextpnr.cc | 28 +++++----- common/route.cc | 12 ++-- common/rulecheck.cc | 14 ++--- generic/arch.cc | 14 ++--- ice40/arch.cc | 12 ++-- ice40/arch.h | 140 ++++++++++++++++++---------------------------- ice40/arch_place.cc | 4 +- ice40/bitstream.cc | 22 ++++---- ice40/cells.cc | 8 +-- ice40/place_legaliser.cc | 12 ++-- ice40/resource/embed.cc | 23 ++++---- ice40/resource/resource.h | 10 ++-- json/jsonparse.cc | 2 +- 14 files changed, 137 insertions(+), 168 deletions(-) diff --git a/common/design_utils.cc b/common/design_utils.cc index 58257bb7..6876babe 100644 --- a/common/design_utils.cc +++ b/common/design_utils.cc @@ -28,7 +28,7 @@ void replace_port(CellInfo *old_cell, IdString old_name, CellInfo *rep_cell, IdS { PortInfo &old = old_cell->ports.at(old_name); PortInfo &rep = rep_cell->ports.at(rep_name); - assert(old.type == rep.type); + NPNR_ASSERT(old.type == rep.type); rep.net = old.net; old.net = nullptr; @@ -47,7 +47,7 @@ void replace_port(CellInfo *old_cell, IdString old_name, CellInfo *rep_cell, IdS } } } else { - assert(false); + NPNR_ASSERT(false); } } diff --git a/common/nextpnr.cc b/common/nextpnr.cc index 40eb2536..a197eaff 100644 --- a/common/nextpnr.cc +++ b/common/nextpnr.cc @@ -47,8 +47,8 @@ const char *IdString::c_str(const BaseCtx *ctx) const { return str(ctx).c_str(); void IdString::initialize_add(const BaseCtx *ctx, const char *s, int idx) { - assert(ctx->idstring_str_to_idx->count(s) == 0); - assert(int(ctx->idstring_idx_to_str->size()) == idx); + NPNR_ASSERT(ctx->idstring_str_to_idx->count(s) == 0); + NPNR_ASSERT(int(ctx->idstring_idx_to_str->size()) == idx); auto insert_rc = ctx->idstring_str_to_idx->insert({s, idx}); ctx->idstring_idx_to_str->push_back(&insert_rc.first->first); } @@ -170,12 +170,12 @@ void Context::check() const { for (auto &n : nets) { auto ni = n.second.get(); - assert(n.first == ni->name); + NPNR_ASSERT(n.first == ni->name); for (auto &w : ni->wires) { - assert(n.first == getBoundWireNet(w.first)); + NPNR_ASSERT(n.first == getBoundWireNet(w.first)); if (w.second.pip != PipId()) { - assert(w.first == getPipDstWire(w.second.pip)); - assert(n.first == getBoundPipNet(w.second.pip)); + NPNR_ASSERT(w.first == getPipDstWire(w.second.pip)); + NPNR_ASSERT(n.first == getBoundPipNet(w.second.pip)); } } } @@ -183,24 +183,24 @@ void Context::check() const for (auto w : getWires()) { IdString net = getBoundWireNet(w); if (net != IdString()) { - assert(nets.at(net)->wires.count(w)); + NPNR_ASSERT(nets.at(net)->wires.count(w)); } } for (auto &c : cells) { - assert(c.first == c.second->name); + NPNR_ASSERT(c.first == c.second->name); if (c.second->bel != BelId()) - assert(getBoundBelCell(c.second->bel) == c.first); + NPNR_ASSERT(getBoundBelCell(c.second->bel) == c.first); for (auto &port : c.second->ports) { NetInfo *net = port.second.net; if (net != nullptr) { - assert(nets.find(net->name) != nets.end()); + NPNR_ASSERT(nets.find(net->name) != nets.end()); if (port.second.type == PORT_OUT) { - assert(net->driver.cell == c.second.get() && net->driver.port == port.first); + NPNR_ASSERT(net->driver.cell == c.second.get() && net->driver.port == port.first); } else if (port.second.type == PORT_IN) { - assert(std::count_if(net->users.begin(), net->users.end(), [&](const PortRef &pr) { - return pr.cell == c.second.get() && pr.port == port.first; - }) == 1); + NPNR_ASSERT(std::count_if(net->users.begin(), net->users.end(), [&](const PortRef &pr) { + return pr.cell == c.second.get() && pr.port == port.first; + }) == 1); } } } diff --git a/common/route.cc b/common/route.cc index 60965f84..82525fcc 100644 --- a/common/route.cc +++ b/common/route.cc @@ -95,7 +95,7 @@ void ripup_net(Context *ctx, IdString net_name) for (auto wire : wires) ctx->unbindWire(wire); - assert(net_info->wires.empty()); + NPNR_ASSERT(net_info->wires.empty()); } struct Router @@ -187,7 +187,7 @@ struct Router if (foundRipupNet) next_delay += ripup_penalty; - assert(next_delay >= 0); + NPNR_ASSERT(next_delay >= 0); if (visited.count(next_wire)) { if (visited.at(next_wire).delay <= next_delay + ctx->getDelayEpsilon()) @@ -358,8 +358,8 @@ struct Router IdString conflicting_wire_net = ctx->getConflictingWireNet(cursor); if (conflicting_wire_net != IdString()) { - assert(ripup); - assert(conflicting_wire_net != net_name); + NPNR_ASSERT(ripup); + NPNR_ASSERT(conflicting_wire_net != net_name); ctx->unbindWire(cursor); if (!ctx->checkWireAvail(cursor)) @@ -375,8 +375,8 @@ struct Router IdString conflicting_pip_net = ctx->getConflictingPipNet(pip); if (conflicting_pip_net != IdString()) { - assert(ripup); - assert(conflicting_pip_net != net_name); + NPNR_ASSERT(ripup); + NPNR_ASSERT(conflicting_pip_net != net_name); ctx->unbindPip(pip); if (!ctx->checkPipAvail(pip)) diff --git a/common/rulecheck.cc b/common/rulecheck.cc index 2570dd65..c696e548 100644 --- a/common/rulecheck.cc +++ b/common/rulecheck.cc @@ -23,18 +23,18 @@ bool check_all_nets_driven(Context *ctx) log_info(" Checking name of port \'%s\' " "against \'%s\'\n", port_entry.first.c_str(ctx), port.name.c_str(ctx)); - assert(port.name == port_entry.first); - assert(!port.name.empty()); + NPNR_ASSERT(port.name == port_entry.first); + NPNR_ASSERT(!port.name.empty()); if (port.net == NULL) { if (debug) log_warning(" Port \'%s\' in cell \'%s\' is unconnected\n", port.name.c_str(ctx), cell->name.c_str(ctx)); } else { - assert(port.net); + NPNR_ASSERT(port.net); if (debug) log_info(" Checking for a net named \'%s\'\n", port.net->name.c_str(ctx)); - assert(ctx->nets.count(port.net->name) > 0); + NPNR_ASSERT(ctx->nets.count(port.net->name) > 0); } } } @@ -42,13 +42,13 @@ bool check_all_nets_driven(Context *ctx) for (auto &net_entry : ctx->nets) { NetInfo *net = net_entry.second.get(); - assert(net->name == net_entry.first); + NPNR_ASSERT(net->name == net_entry.first); if ((net->driver.cell != NULL) && (net->driver.cell->type != ctx->id("GND")) && (net->driver.cell->type != ctx->id("VCC"))) { if (debug) log_info(" Checking for a driver cell named \'%s\'\n", net->driver.cell->name.c_str(ctx)); - assert(ctx->cells.count(net->driver.cell->name) > 0); + NPNR_ASSERT(ctx->cells.count(net->driver.cell->name) > 0); } for (auto user : net->users) { @@ -56,7 +56,7 @@ bool check_all_nets_driven(Context *ctx) if (debug) log_info(" Checking for a user cell named \'%s\'\n", user.cell->name.c_str(ctx)); - assert(ctx->cells.count(user.cell->name) > 0); + NPNR_ASSERT(ctx->cells.count(user.cell->name) > 0); } } } diff --git a/generic/arch.cc b/generic/arch.cc index 16fe2935..8f897604 100644 --- a/generic/arch.cc +++ b/generic/arch.cc @@ -24,7 +24,7 @@ NEXTPNR_NAMESPACE_BEGIN void Arch::addWire(IdString name, int x, int y) { - assert(wires.count(name) == 0); + NPNR_ASSERT(wires.count(name) == 0); WireInfo &wi = wires[name]; wi.name = name; wi.grid_x = x; @@ -35,7 +35,7 @@ void Arch::addWire(IdString name, int x, int y) void Arch::addPip(IdString name, IdString srcWire, IdString dstWire, DelayInfo delay) { - assert(pips.count(name) == 0); + NPNR_ASSERT(pips.count(name) == 0); PipInfo &pi = pips[name]; pi.name = name; pi.srcWire = srcWire; @@ -49,7 +49,7 @@ void Arch::addPip(IdString name, IdString srcWire, IdString dstWire, DelayInfo d void Arch::addAlias(IdString name, IdString srcWire, IdString dstWire, DelayInfo delay) { - assert(pips.count(name) == 0); + NPNR_ASSERT(pips.count(name) == 0); PipInfo &pi = pips[name]; pi.name = name; pi.srcWire = srcWire; @@ -62,7 +62,7 @@ void Arch::addAlias(IdString name, IdString srcWire, IdString dstWire, DelayInfo void Arch::addBel(IdString name, IdString type, int x, int y, bool gb) { - assert(bels.count(name) == 0); + NPNR_ASSERT(bels.count(name) == 0); BelInfo &bi = bels[name]; bi.name = name; bi.type = type; @@ -76,7 +76,7 @@ void Arch::addBel(IdString name, IdString type, int x, int y, bool gb) void Arch::addBelInput(IdString bel, IdString name, IdString wire) { - assert(bels.at(bel).pins.count(name) == 0); + NPNR_ASSERT(bels.at(bel).pins.count(name) == 0); PinInfo &pi = bels.at(bel).pins[name]; pi.name = name; pi.wire = wire; @@ -87,7 +87,7 @@ void Arch::addBelInput(IdString bel, IdString name, IdString wire) void Arch::addBelOutput(IdString bel, IdString name, IdString wire) { - assert(bels.at(bel).pins.count(name) == 0); + NPNR_ASSERT(bels.at(bel).pins.count(name) == 0); PinInfo &pi = bels.at(bel).pins[name]; pi.name = name; pi.wire = wire; @@ -98,7 +98,7 @@ void Arch::addBelOutput(IdString bel, IdString name, IdString wire) void Arch::addBelInout(IdString bel, IdString name, IdString wire) { - assert(bels.at(bel).pins.count(name) == 0); + NPNR_ASSERT(bels.at(bel).pins.count(name) == 0); PinInfo &pi = bels.at(bel).pins[name]; pi.name = name; pi.wire = wire; diff --git a/ice40/arch.cc b/ice40/arch.cc index c2d93472..72f9c1f3 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -254,7 +254,7 @@ BelId Arch::getBelByName(IdString name) const BelRange Arch::getBelsAtSameTile(BelId bel) const { BelRange br; - assert(bel != BelId()); + NPNR_ASSERT(bel != BelId()); // This requires Bels at the same tile are consecutive int x = chip_info->bel_data[bel.index].x; int y = chip_info->bel_data[bel.index].y; @@ -273,7 +273,7 @@ WireId Arch::getWireBelPin(BelId bel, PortPin pin) const { WireId ret; - assert(bel != BelId()); + NPNR_ASSERT(bel != BelId()); int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires; const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get(); @@ -328,7 +328,7 @@ PipId Arch::getPipByName(IdString name) const IdString Arch::getPipName(PipId pip) const { - assert(pip != PipId()); + NPNR_ASSERT(pip != PipId()); int x = chip_info->pip_data[pip.index].x; int y = chip_info->pip_data[pip.index].y; @@ -369,7 +369,7 @@ std::string Arch::getBelPackagePin(BelId bel) const void Arch::estimatePosition(BelId bel, int &x, int &y, bool &gb) const { - assert(bel != BelId()); + NPNR_ASSERT(bel != BelId()); x = chip_info->bel_data[bel.index].x; y = chip_info->bel_data[bel.index].y; gb = chip_info->bel_data[bel.index].type == TYPE_SB_GB; @@ -377,11 +377,11 @@ void Arch::estimatePosition(BelId bel, int &x, int &y, bool &gb) const delay_t Arch::estimateDelay(WireId src, WireId dst) const { - assert(src != WireId()); + NPNR_ASSERT(src != WireId()); int x1 = chip_info->wire_data[src.index].x; int y1 = chip_info->wire_data[src.index].y; - assert(dst != WireId()); + NPNR_ASSERT(dst != WireId()); int x2 = chip_info->wire_data[dst.index].x; int y2 = chip_info->wire_data[dst.index].y; diff --git a/ice40/arch.h b/ice40/arch.h index cd14949f..c91625e9 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -43,16 +43,12 @@ template struct RelPtr const T *operator->() const { return get(); } }; -NPNR_PACKED_STRUCT( -struct BelWirePOD -{ +NPNR_PACKED_STRUCT(struct BelWirePOD { int32_t wire_index; PortPin port; }); -NPNR_PACKED_STRUCT( -struct BelInfoPOD -{ +NPNR_PACKED_STRUCT(struct BelInfoPOD { RelPtr name; BelType type; int32_t num_bel_wires; @@ -61,16 +57,12 @@ struct BelInfoPOD int8_t padding_0; }); -NPNR_PACKED_STRUCT( -struct BelPortPOD -{ +NPNR_PACKED_STRUCT(struct BelPortPOD { int32_t bel_index; PortPin port; }); -NPNR_PACKED_STRUCT( -struct PipInfoPOD -{ +NPNR_PACKED_STRUCT(struct PipInfoPOD { int32_t src, dst; int32_t delay; int8_t x, y; @@ -78,9 +70,7 @@ struct PipInfoPOD int32_t switch_index; }); -NPNR_PACKED_STRUCT( -struct WireInfoPOD -{ +NPNR_PACKED_STRUCT(struct WireInfoPOD { RelPtr name; int32_t num_uphill, num_downhill; RelPtr pips_uphill, pips_downhill; @@ -94,16 +84,12 @@ struct WireInfoPOD int8_t padding_0; }); -NPNR_PACKED_STRUCT( -struct PackagePinPOD -{ +NPNR_PACKED_STRUCT(struct PackagePinPOD { RelPtr name; int32_t bel_index; }); -NPNR_PACKED_STRUCT( -struct PackageInfoPOD -{ +NPNR_PACKED_STRUCT(struct PackageInfoPOD { RelPtr name; int32_t num_pins; RelPtr pins; @@ -123,23 +109,15 @@ enum TileType : uint32_t TILE_IPCON = 9 }; -NPNR_PACKED_STRUCT( -struct ConfigBitPOD -{ - int8_t row, col; -}); +NPNR_PACKED_STRUCT(struct ConfigBitPOD { int8_t row, col; }); -NPNR_PACKED_STRUCT( -struct ConfigEntryPOD -{ +NPNR_PACKED_STRUCT(struct ConfigEntryPOD { RelPtr name; int32_t num_bits; RelPtr bits; }); -NPNR_PACKED_STRUCT( -struct TileInfoPOD -{ +NPNR_PACKED_STRUCT(struct TileInfoPOD { int8_t cols, rows; int16_t num_config_entries; RelPtr entries; @@ -147,33 +125,25 @@ struct TileInfoPOD static const int max_switch_bits = 5; -NPNR_PACKED_STRUCT( -struct SwitchInfoPOD -{ +NPNR_PACKED_STRUCT(struct SwitchInfoPOD { int32_t num_bits; int8_t x, y; ConfigBitPOD cbits[max_switch_bits]; }); -NPNR_PACKED_STRUCT( -struct IerenInfoPOD -{ +NPNR_PACKED_STRUCT(struct IerenInfoPOD { int8_t iox, ioy, ioz; int8_t ierx, iery, ierz; }); -NPNR_PACKED_STRUCT( -struct BitstreamInfoPOD -{ +NPNR_PACKED_STRUCT(struct BitstreamInfoPOD { int32_t num_switches, num_ierens; RelPtr tiles_nonrouting; RelPtr switches; RelPtr ierens; }); -NPNR_PACKED_STRUCT( -struct ChipInfoPOD -{ +NPNR_PACKED_STRUCT(struct ChipInfoPOD { int32_t width, height; int32_t num_bels, num_wires, num_pips; int32_t num_switches, num_packages; @@ -186,10 +156,10 @@ struct ChipInfoPOD }); #if defined(_MSC_VER) -extern const char* chipdb_blob_384; -extern const char* chipdb_blob_1k; -extern const char* chipdb_blob_5k; -extern const char* chipdb_blob_8k; +extern const char *chipdb_blob_384; +extern const char *chipdb_blob_1k; +extern const char *chipdb_blob_5k; +extern const char *chipdb_blob_8k; #else extern const char chipdb_blob_384[]; extern const char chipdb_blob_1k[]; @@ -380,7 +350,7 @@ struct Arch : BaseCtx IdString getBelName(BelId bel) const { - assert(bel != BelId()); + NPNR_ASSERT(bel != BelId()); return id(chip_info->bel_data[bel.index].name.get()); } @@ -388,8 +358,8 @@ struct Arch : BaseCtx void bindBel(BelId bel, IdString cell, PlaceStrength strength) { - assert(bel != BelId()); - assert(bel_to_cell[bel.index] == IdString()); + NPNR_ASSERT(bel != BelId()); + NPNR_ASSERT(bel_to_cell[bel.index] == IdString()); bel_to_cell[bel.index] = cell; cells[cell]->bel = bel; cells[cell]->belStrength = strength; @@ -397,8 +367,8 @@ struct Arch : BaseCtx void unbindBel(BelId bel) { - assert(bel != BelId()); - assert(bel_to_cell[bel.index] != IdString()); + NPNR_ASSERT(bel != BelId()); + NPNR_ASSERT(bel_to_cell[bel.index] != IdString()); cells[bel_to_cell[bel.index]]->bel = BelId(); cells[bel_to_cell[bel.index]]->belStrength = STRENGTH_NONE; bel_to_cell[bel.index] = IdString(); @@ -406,19 +376,19 @@ struct Arch : BaseCtx bool checkBelAvail(BelId bel) const { - assert(bel != BelId()); + NPNR_ASSERT(bel != BelId()); return bel_to_cell[bel.index] == IdString(); } IdString getBoundBelCell(BelId bel) const { - assert(bel != BelId()); + NPNR_ASSERT(bel != BelId()); return bel_to_cell[bel.index]; } IdString getConflictingBelCell(BelId bel) const { - assert(bel != BelId()); + NPNR_ASSERT(bel != BelId()); return bel_to_cell[bel.index]; } @@ -448,7 +418,7 @@ struct Arch : BaseCtx BelType getBelType(BelId bel) const { - assert(bel != BelId()); + NPNR_ASSERT(bel != BelId()); return chip_info->bel_data[bel.index].type; } @@ -457,7 +427,7 @@ struct Arch : BaseCtx BelPin getBelPinUphill(WireId wire) const { BelPin ret; - assert(wire != WireId()); + NPNR_ASSERT(wire != WireId()); if (chip_info->wire_data[wire.index].bel_uphill.bel_index >= 0) { ret.bel.index = chip_info->wire_data[wire.index].bel_uphill.bel_index; @@ -470,7 +440,7 @@ struct Arch : BaseCtx BelPinRange getBelPinsDownhill(WireId wire) const { BelPinRange range; - assert(wire != WireId()); + NPNR_ASSERT(wire != WireId()); range.b.ptr = chip_info->wire_data[wire.index].bels_downhill.get(); range.e.ptr = range.b.ptr + chip_info->wire_data[wire.index].num_bels_downhill; return range; @@ -482,7 +452,7 @@ struct Arch : BaseCtx IdString getWireName(WireId wire) const { - assert(wire != WireId()); + NPNR_ASSERT(wire != WireId()); return id(chip_info->wire_data[wire.index].name.get()); } @@ -490,8 +460,8 @@ struct Arch : BaseCtx void bindWire(WireId wire, IdString net, PlaceStrength strength) { - assert(wire != WireId()); - assert(wire_to_net[wire.index] == IdString()); + NPNR_ASSERT(wire != WireId()); + NPNR_ASSERT(wire_to_net[wire.index] == IdString()); wire_to_net[wire.index] = net; nets[net]->wires[wire].pip = PipId(); nets[net]->wires[wire].strength = strength; @@ -499,12 +469,12 @@ struct Arch : BaseCtx void unbindWire(WireId wire) { - assert(wire != WireId()); - assert(wire_to_net[wire.index] != IdString()); + NPNR_ASSERT(wire != WireId()); + NPNR_ASSERT(wire_to_net[wire.index] != IdString()); auto &net_wires = nets[wire_to_net[wire.index]]->wires; auto it = net_wires.find(wire); - assert(it != net_wires.end()); + NPNR_ASSERT(it != net_wires.end()); auto pip = it->second.pip; if (pip != PipId()) { @@ -518,19 +488,19 @@ struct Arch : BaseCtx bool checkWireAvail(WireId wire) const { - assert(wire != WireId()); + NPNR_ASSERT(wire != WireId()); return wire_to_net[wire.index] == IdString(); } IdString getBoundWireNet(WireId wire) const { - assert(wire != WireId()); + NPNR_ASSERT(wire != WireId()); return wire_to_net[wire.index]; } IdString getConflictingWireNet(WireId wire) const { - assert(wire != WireId()); + NPNR_ASSERT(wire != WireId()); return wire_to_net[wire.index]; } @@ -551,16 +521,16 @@ struct Arch : BaseCtx void bindPip(PipId pip, IdString net, PlaceStrength strength) { - assert(pip != PipId()); - assert(pip_to_net[pip.index] == IdString()); - assert(switches_locked[chip_info->pip_data[pip.index].switch_index] == IdString()); + NPNR_ASSERT(pip != PipId()); + NPNR_ASSERT(pip_to_net[pip.index] == IdString()); + NPNR_ASSERT(switches_locked[chip_info->pip_data[pip.index].switch_index] == IdString()); pip_to_net[pip.index] = net; switches_locked[chip_info->pip_data[pip.index].switch_index] = net; WireId dst; dst.index = chip_info->pip_data[pip.index].dst; - assert(wire_to_net[dst.index] == IdString()); + NPNR_ASSERT(wire_to_net[dst.index] == IdString()); wire_to_net[dst.index] = net; nets[net]->wires[dst].pip = pip; nets[net]->wires[dst].strength = strength; @@ -568,13 +538,13 @@ struct Arch : BaseCtx void unbindPip(PipId pip) { - assert(pip != PipId()); - assert(pip_to_net[pip.index] != IdString()); - assert(switches_locked[chip_info->pip_data[pip.index].switch_index] != IdString()); + NPNR_ASSERT(pip != PipId()); + NPNR_ASSERT(pip_to_net[pip.index] != IdString()); + NPNR_ASSERT(switches_locked[chip_info->pip_data[pip.index].switch_index] != IdString()); WireId dst; dst.index = chip_info->pip_data[pip.index].dst; - assert(wire_to_net[dst.index] != IdString()); + NPNR_ASSERT(wire_to_net[dst.index] != IdString()); wire_to_net[dst.index] = IdString(); nets[pip_to_net[pip.index]]->wires.erase(dst); @@ -584,19 +554,19 @@ struct Arch : BaseCtx bool checkPipAvail(PipId pip) const { - assert(pip != PipId()); + NPNR_ASSERT(pip != PipId()); return switches_locked[chip_info->pip_data[pip.index].switch_index] == IdString(); } IdString getBoundPipNet(PipId pip) const { - assert(pip != PipId()); + NPNR_ASSERT(pip != PipId()); return pip_to_net[pip.index]; } IdString getConflictingPipNet(PipId pip) const { - assert(pip != PipId()); + NPNR_ASSERT(pip != PipId()); return switches_locked[chip_info->pip_data[pip.index].switch_index]; } @@ -611,7 +581,7 @@ struct Arch : BaseCtx WireId getPipSrcWire(PipId pip) const { WireId wire; - assert(pip != PipId()); + NPNR_ASSERT(pip != PipId()); wire.index = chip_info->pip_data[pip.index].src; return wire; } @@ -619,7 +589,7 @@ struct Arch : BaseCtx WireId getPipDstWire(PipId pip) const { WireId wire; - assert(pip != PipId()); + NPNR_ASSERT(pip != PipId()); wire.index = chip_info->pip_data[pip.index].dst; return wire; } @@ -627,7 +597,7 @@ struct Arch : BaseCtx DelayInfo getPipDelay(PipId pip) const { DelayInfo delay; - assert(pip != PipId()); + NPNR_ASSERT(pip != PipId()); delay.delay = chip_info->pip_data[pip.index].delay; return delay; } @@ -635,7 +605,7 @@ struct Arch : BaseCtx PipRange getPipsDownhill(WireId wire) const { PipRange range; - assert(wire != WireId()); + NPNR_ASSERT(wire != WireId()); range.b.cursor = chip_info->wire_data[wire.index].pips_downhill.get(); range.e.cursor = range.b.cursor + chip_info->wire_data[wire.index].num_downhill; return range; @@ -644,7 +614,7 @@ struct Arch : BaseCtx PipRange getPipsUphill(WireId wire) const { PipRange range; - assert(wire != WireId()); + NPNR_ASSERT(wire != WireId()); range.b.cursor = chip_info->wire_data[wire.index].pips_uphill.get(); range.e.cursor = range.b.cursor + chip_info->wire_data[wire.index].num_uphill; return range; @@ -653,7 +623,7 @@ struct Arch : BaseCtx PipRange getWireAliases(WireId wire) const { PipRange range; - assert(wire != WireId()); + NPNR_ASSERT(wire != WireId()); range.b.cursor = nullptr; range.e.cursor = nullptr; return range; diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc index adc90f2f..dc1bc3eb 100644 --- a/ice40/arch_place.cc +++ b/ice40/arch_place.cc @@ -99,7 +99,7 @@ bool Arch::isBelLocationValid(BelId bel) const bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const { if (cell->type == id_icestorm_lc) { - assert(getBelType(bel) == TYPE_ICESTORM_LC); + NPNR_ASSERT(getBelType(bel) == TYPE_ICESTORM_LC); std::vector bel_cells; @@ -117,7 +117,7 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const return getBelPackagePin(bel) != ""; } else if (cell->type == id_sb_gb) { bool is_reset = false, is_cen = false; - assert(cell->ports.at(id_glb_buf_out).net != nullptr); + NPNR_ASSERT(cell->ports.at(id_glb_buf_out).net != nullptr); for (auto user : cell->ports.at(id_glb_buf_out).net->users) { if (is_reset_port(this, user)) is_reset = true; diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index c739d3c9..33c4d97b 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -36,7 +36,7 @@ const ConfigEntryPOD &find_config(const TileInfoPOD &tile, const std::string &na return tile.entries[i]; } } - assert(false); + NPNR_ASSERT(false); } std::tuple get_ieren(const BitstreamInfoPOD &bi, int8_t x, int8_t y, int8_t z) @@ -124,7 +124,7 @@ void write_asc(const Context *ctx, std::ostream &out) out << ".device 5k" << std::endl; break; default: - assert(false); + NPNR_ASSERT(false); } // Set pips for (auto pip : ctx->getPips()) { @@ -135,7 +135,7 @@ void write_asc(const Context *ctx, std::ostream &out) bool val = (pi.switch_mask & (1 << ((swi.num_bits - 1) - i))) != 0; int8_t &cbit = config.at(swi.y).at(swi.x).at(swi.cbits[i].row).at(swi.cbits[i].col); if (bool(cbit) != 0) - assert(false); + NPNR_ASSERT(false); cbit = val; } } @@ -180,7 +180,7 @@ void write_asc(const Context *ctx, std::ostream &out) bool carry_set = get_param_or_def(cell.second.get(), ctx->id("CIN_SET")); if (carry_const) { if (!ctx->force) - assert(z == 0); + NPNR_ASSERT(z == 0); set_config(ti, config.at(y).at(x), "CarryInSet", carry_set); } } else if (cell.second->type == ctx->id("SB_IO")) { @@ -196,7 +196,7 @@ void write_asc(const Context *ctx, std::ostream &out) auto ieren = get_ieren(bi, x, y, z); int iex, iey, iez; std::tie(iex, iey, iez) = ieren; - assert(iez != -1); + NPNR_ASSERT(iez != -1); bool input_en = false; if ((ctx->wire_to_net[ctx->getWireBelPin(bel, PIN_D_IN_0).index] != IdString()) || @@ -245,7 +245,7 @@ void write_asc(const Context *ctx, std::ostream &out) } else if (cell.second->type == ctx->id("ICESTORM_SPRAM")) { const BelInfoPOD &beli = ci.bel_data[bel.index]; int x = beli.x, y = beli.y, z = beli.z; - assert(ctx->args.type == ArchArgs::UP5K); + NPNR_ASSERT(ctx->args.type == ArchArgs::UP5K); if (x == 0 && y == 0) { const TileInfoPOD &ti_ipcon = bi.tiles_nonrouting[TILE_IPCON]; if (z == 1) { @@ -253,7 +253,7 @@ void write_asc(const Context *ctx, std::ostream &out) } else if (z == 2) { set_config(ti_ipcon, config.at(1).at(0), "IpConfig.CBIT_1", true); } else { - assert(false); + NPNR_ASSERT(false); } } else if (x == 25 && y == 0) { const TileInfoPOD &ti_ipcon = bi.tiles_nonrouting[TILE_IPCON]; @@ -262,11 +262,11 @@ void write_asc(const Context *ctx, std::ostream &out) } else if (z == 4) { set_config(ti_ipcon, config.at(1).at(25), "IpConfig.CBIT_1", true); } else { - assert(false); + NPNR_ASSERT(false); } } } else { - assert(false); + NPNR_ASSERT(false); } } // Set config bits in unused IO and RAM @@ -386,7 +386,7 @@ void write_asc(const Context *ctx, std::ostream &out) out << ".ipcon_tile"; break; default: - assert(false); + NPNR_ASSERT(false); } out << " " << x << " " << y << std::endl; for (auto row : config.at(y).at(x)) { @@ -413,7 +413,7 @@ void write_asc(const Context *ctx, std::ostream &out) std::vector bits(256); std::string init = get_param_str_or_def(cell.second.get(), ctx->id(std::string("INIT_") + get_hexdigit(w))); - assert(init != ""); + NPNR_ASSERT(init != ""); for (size_t i = 0; i < init.size(); i++) { bool val = (init.at((init.size() - 1) - i) == '1'); bits.at(i) = val; diff --git a/ice40/cells.cc b/ice40/cells.cc index 7f690930..1ba40970 100644 --- a/ice40/cells.cc +++ b/ice40/cells.cc @@ -183,7 +183,7 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l if (citer != config.end()) { if ((config.end() - citer) >= 2) { char c = *(citer++); - assert(c == 'S'); + NPNR_ASSERT(c == 'S'); lc->params[ctx->id("ASYNC_SR")] = "0"; } else { lc->params[ctx->id("ASYNC_SR")] = "1"; @@ -194,14 +194,14 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l replace_port(dff, ctx->id("S"), lc, ctx->id("SR")); lc->params[ctx->id("SET_NORESET")] = "1"; } else { - assert(*citer == 'R'); + NPNR_ASSERT(*citer == 'R'); citer++; replace_port(dff, ctx->id("R"), lc, ctx->id("SR")); lc->params[ctx->id("SET_NORESET")] = "0"; } } - assert(citer == config.end()); + NPNR_ASSERT(citer == config.end()); if (pass_thru_lut) { lc->params[ctx->id("LUT_INIT")] = "2"; @@ -228,7 +228,7 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio) replace_port(nxio, ctx->id("I"), sbio, ctx->id("D_OUT_0")); replace_port(nxio, ctx->id("O"), sbio, ctx->id("D_IN_0")); } else { - assert(false); + NPNR_ASSERT(false); } NetInfo *donet = sbio->ports.at(ctx->id("D_OUT_0")).net; CellInfo *tbuf = net_driven_by( diff --git a/ice40/place_legaliser.cc b/ice40/place_legaliser.cc index b141148b..559358c7 100644 --- a/ice40/place_legaliser.cc +++ b/ice40/place_legaliser.cc @@ -82,7 +82,7 @@ static void get_chain_midpoint(const Context *ctx, const CellChain &chain, float total_y += bel_y; N++; } - assert(N > 0); + NPNR_ASSERT(N > 0); x = total_x / N; y = total_y / N; } @@ -328,7 +328,7 @@ class PlacementLegaliser void place_lc(CellInfo *cell, int x, int y, int z) { auto &loc = logic_bels.at(x).at(y).at(z); - assert(!loc.second); + NPNR_ASSERT(!loc.second); BelId bel = loc.first; // Check if there is a cell presently at the location, which we will need to rip up IdString existing = ctx->getBoundBelCell(bel); @@ -348,7 +348,7 @@ class PlacementLegaliser // Insert a logic cell to legalise a COUT->fabric connection CellInfo *make_carry_pass_out(PortInfo &cout_port) { - assert(cout_port.net != nullptr); + NPNR_ASSERT(cout_port.net != nullptr); std::unique_ptr lc = create_ice_cell(ctx, ctx->id("ICESTORM_LC")); lc->params[ctx->id("LUT_INIT")] = "65280"; // 0xff00: O = I3 lc->params[ctx->id("CARRY_ENABLE")] = "1"; @@ -368,7 +368,7 @@ class PlacementLegaliser cout_port.net = co_i3_net.get(); IdString co_i3_name = co_i3_net->name; - assert(ctx->nets.find(co_i3_name) == ctx->nets.end()); + NPNR_ASSERT(ctx->nets.find(co_i3_name) == ctx->nets.end()); ctx->nets[co_i3_name] = std::move(co_i3_net); IdString name = lc->name; ctx->cells[lc->name] = std::move(lc); @@ -379,7 +379,7 @@ class PlacementLegaliser // Insert a logic cell to legalise a CIN->fabric connection CellInfo *make_carry_feed_in(CellInfo *cin_cell, PortInfo &cin_port) { - assert(cin_port.net != nullptr); + NPNR_ASSERT(cin_port.net != nullptr); std::unique_ptr lc = create_ice_cell(ctx, ctx->id("ICESTORM_LC")); lc->params[ctx->id("CARRY_ENABLE")] = "1"; lc->params[ctx->id("CIN_CONST")] = "1"; @@ -411,7 +411,7 @@ class PlacementLegaliser cin_cell->ports.at(cin_port.name).net = out_net.get(); IdString out_net_name = out_net->name; - assert(ctx->nets.find(out_net_name) == ctx->nets.end()); + NPNR_ASSERT(ctx->nets.find(out_net_name) == ctx->nets.end()); ctx->nets[out_net_name] = std::move(out_net); IdString name = lc->name; diff --git a/ice40/resource/embed.cc b/ice40/resource/embed.cc index 15245355..74f2eee9 100644 --- a/ice40/resource/embed.cc +++ b/ice40/resource/embed.cc @@ -1,31 +1,30 @@ -#include #include +#include #include "nextpnr.h" #include "resource.h" NEXTPNR_NAMESPACE_BEGIN -const char* chipdb_blob_384; -const char* chipdb_blob_1k; -const char* chipdb_blob_5k; -const char* chipdb_blob_8k; +const char *chipdb_blob_384; +const char *chipdb_blob_1k; +const char *chipdb_blob_5k; +const char *chipdb_blob_8k; -const char* LoadFileInResource(int name, int type, DWORD& size) +const char *LoadFileInResource(int name, int type, DWORD &size) { HMODULE handle = ::GetModuleHandle(NULL); - HRSRC rc = ::FindResource(handle, MAKEINTRESOURCE(name), - MAKEINTRESOURCE(type)); + HRSRC rc = ::FindResource(handle, MAKEINTRESOURCE(name), MAKEINTRESOURCE(type)); HGLOBAL rcData = ::LoadResource(handle, rc); size = ::SizeofResource(handle, rc); - return static_cast(::LockResource(rcData)); + return static_cast(::LockResource(rcData)); } void load_chipdb() { DWORD size = 0; chipdb_blob_384 = LoadFileInResource(IDR_CHIPDB_384, BINARYFILE, size); - chipdb_blob_1k = LoadFileInResource(IDR_CHIPDB_1K, BINARYFILE, size); - chipdb_blob_5k = LoadFileInResource(IDR_CHIPDB_5K, BINARYFILE, size); - chipdb_blob_8k = LoadFileInResource(IDR_CHIPDB_8K, BINARYFILE, size); + chipdb_blob_1k = LoadFileInResource(IDR_CHIPDB_1K, BINARYFILE, size); + chipdb_blob_5k = LoadFileInResource(IDR_CHIPDB_5K, BINARYFILE, size); + chipdb_blob_8k = LoadFileInResource(IDR_CHIPDB_8K, BINARYFILE, size); } NEXTPNR_NAMESPACE_END \ No newline at end of file diff --git a/ice40/resource/resource.h b/ice40/resource/resource.h index 8348fea1..46997ae5 100644 --- a/ice40/resource/resource.h +++ b/ice40/resource/resource.h @@ -1,5 +1,5 @@ -#define BINARYFILE 256 -#define IDR_CHIPDB_384 101 -#define IDR_CHIPDB_1K 102 -#define IDR_CHIPDB_5K 103 -#define IDR_CHIPDB_8K 104 +#define BINARYFILE 256 +#define IDR_CHIPDB_384 101 +#define IDR_CHIPDB_1K 102 +#define IDR_CHIPDB_5K 103 +#define IDR_CHIPDB_8K 104 diff --git a/json/jsonparse.cc b/json/jsonparse.cc index bf1760d3..3bcbe285 100644 --- a/json/jsonparse.cc +++ b/json/jsonparse.cc @@ -25,10 +25,10 @@ #include #include #include +#include #include #include #include -#include #include "nextpnr.h" NEXTPNR_NAMESPACE_BEGIN -- cgit v1.2.3