From 6aaa9f5a3d02224f2760d993d114163ce7678e1f Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 13 Nov 2019 12:11:17 +0000 Subject: frontend/base: Functions for port import Signed-off-by: David Shah --- common/nextpnr.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'common/nextpnr.h') diff --git a/common/nextpnr.h b/common/nextpnr.h index 24f6948b..3fce97a2 100644 --- a/common/nextpnr.h +++ b/common/nextpnr.h @@ -397,6 +397,8 @@ struct NetInfo : ArchNetInfo // wire -> uphill_pip std::unordered_map wires; + std::vector aliases; // entries in net_aliases that point to this net + std::unique_ptr clkconstr; TimingConstrObjectId tmg_id; -- cgit v1.2.3 From 6bf3c261fa3e13319430380096aca65042476ae3 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 28 Nov 2019 20:45:49 +0000 Subject: First pass at data structures for hierarchy Signed-off-by: David Shah --- common/nextpnr.h | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) (limited to 'common/nextpnr.h') diff --git a/common/nextpnr.h b/common/nextpnr.h index 3fce97a2..ceea2088 100644 --- a/common/nextpnr.h +++ b/common/nextpnr.h @@ -387,7 +387,7 @@ struct ClockConstraint; struct NetInfo : ArchNetInfo { - IdString name; + IdString name, hierpath; int32_t udata = 0; PortRef driver; @@ -423,7 +423,7 @@ struct PortInfo struct CellInfo : ArchCellInfo { - IdString name, type; + IdString name, type, hierpath; int32_t udata; std::unordered_map ports; @@ -527,6 +527,28 @@ struct TimingConstraint std::unordered_set to; }; +// Represents the contents of a non-leaf cell in a design +// with hierarchy + +struct HierachicalPort +{ + IdString name; + PortType dir; + std::vector nets; + int offset; + bool upto; +}; + +struct HierachicalCell +{ + IdString name, type, parent, fullpath; + // Name inside cell instance -> global name + std::unordered_map leaf_cells, nets; + std::unordered_map ports; + // Name inside cell instance -> global name + std::unordered_map hier_cells; +}; + inline bool operator==(const std::pair &a, const std::pair &b) { @@ -620,6 +642,11 @@ struct BaseCtx std::unordered_map> nets; std::unordered_map> cells; + // Hierarchical (non-leaf) cells by full path + std::unordered_map hierarchy; + // This is the root of the above structure + IdString top_module; + // Aliases for nets, which may have more than one name due to assignments and hierarchy std::unordered_map net_aliases; -- cgit v1.2.3 From b1000870244dbb1a73198e23a859825865938b4c Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 29 Nov 2019 16:25:11 +0000 Subject: python: Add bindings for hierarchy structures Signed-off-by: David Shah --- common/nextpnr.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'common/nextpnr.h') diff --git a/common/nextpnr.h b/common/nextpnr.h index ceea2088..7dfebd62 100644 --- a/common/nextpnr.h +++ b/common/nextpnr.h @@ -530,7 +530,7 @@ struct TimingConstraint // Represents the contents of a non-leaf cell in a design // with hierarchy -struct HierachicalPort +struct HierarchicalPort { IdString name; PortType dir; @@ -539,12 +539,12 @@ struct HierachicalPort bool upto; }; -struct HierachicalCell +struct HierarchicalCell { IdString name, type, parent, fullpath; // Name inside cell instance -> global name std::unordered_map leaf_cells, nets; - std::unordered_map ports; + std::unordered_map ports; // Name inside cell instance -> global name std::unordered_map hier_cells; }; @@ -643,7 +643,7 @@ struct BaseCtx std::unordered_map> cells; // Hierarchical (non-leaf) cells by full path - std::unordered_map hierarchy; + std::unordered_map hierarchy; // This is the root of the above structure IdString top_module; -- cgit v1.2.3 From fe40094216d0007797c51ff8894127b37a4ff045 Mon Sep 17 00:00:00 2001 From: David Shah Date: Sun, 1 Dec 2019 14:03:23 +0000 Subject: Preserve hierarchy through packing Signed-off-by: David Shah --- common/nextpnr.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'common/nextpnr.h') diff --git a/common/nextpnr.h b/common/nextpnr.h index 7dfebd62..61e04415 100644 --- a/common/nextpnr.h +++ b/common/nextpnr.h @@ -544,6 +544,9 @@ struct HierarchicalCell IdString name, type, parent, fullpath; // Name inside cell instance -> global name std::unordered_map leaf_cells, nets; + // Global name -> name inside cell instance + std::unordered_map leaf_cells_by_gname, nets_by_gname; + // Cell port to net std::unordered_map ports; // Name inside cell instance -> global name std::unordered_map hier_cells; @@ -835,6 +838,10 @@ struct Context : Arch, DeterministicRNG bool getActualRouteDelay(WireId src_wire, WireId dst_wire, delay_t *delay = nullptr, std::unordered_map *route = nullptr, bool useEstimate = true); + // -------------------------------------------------------------- + // call after changing hierpath or adding/removing nets and cells + void fixupHierarchy(); + // -------------------------------------------------------------- // provided by sdf.cc -- cgit v1.2.3