From 6bd3dba1e39780e52097533f7e89f823d7e72956 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Wed, 10 Feb 2021 10:42:26 +0000
Subject: Remove the unused CellInfo::pins field

No arches ever actually used this to implement a Cell->Bel pin mapping,
and in practice if any did try they would inevitably hit bitrot.

This field had limited use in practice as it is necessary to also
support cases where one cell pin maps to more than one bel pin. Removing
this old field is the first step towards developing a new API for this.

Signed-off-by: gatecat <gatecat@ds0.me>
---
 common/nextpnr.cc    | 20 --------------------
 common/nextpnr.h     |  3 ---
 common/pybindings.cc |  2 --
 3 files changed, 25 deletions(-)

(limited to 'common')

diff --git a/common/nextpnr.cc b/common/nextpnr.cc
index fc70465c..880e0344 100644
--- a/common/nextpnr.cc
+++ b/common/nextpnr.cc
@@ -355,11 +355,6 @@ WireId Context::getNetinfoSourceWire(const NetInfo *net_info) const
         return WireId();
 
     IdString driver_port = net_info->driver.port;
-
-    auto driver_port_it = net_info->driver.cell->pins.find(driver_port);
-    if (driver_port_it != net_info->driver.cell->pins.end())
-        driver_port = driver_port_it->second;
-
     return getBelPinWire(src_bel, driver_port);
 }
 
@@ -371,12 +366,6 @@ WireId Context::getNetinfoSinkWire(const NetInfo *net_info, const PortRef &user_
         return WireId();
 
     IdString user_port = user_info.port;
-
-    auto user_port_it = user_info.cell->pins.find(user_port);
-
-    if (user_port_it != user_info.cell->pins.end())
-        user_port = user_port_it->second;
-
     return getBelPinWire(dst_bel, user_port);
 }
 
@@ -516,15 +505,6 @@ uint32_t Context::checksum() const
         x = xorshift32(x + xorshift32(getBelChecksum(ci.bel)));
         x = xorshift32(x + xorshift32(ci.belStrength));
 
-        uint32_t pin_x_sum = 0;
-        for (auto &a : ci.pins) {
-            uint32_t pin_x = 123456789;
-            pin_x = xorshift32(pin_x + xorshift32(a.first.index));
-            pin_x = xorshift32(pin_x + xorshift32(a.second.index));
-            pin_x_sum += pin_x;
-        }
-        x = xorshift32(x + xorshift32(pin_x_sum));
-
         cksum_cells_sum += x;
     }
     cksum = xorshift32(cksum + xorshift32(cksum_cells_sum));
diff --git a/common/nextpnr.h b/common/nextpnr.h
index 12462698..c43b9dc4 100644
--- a/common/nextpnr.h
+++ b/common/nextpnr.h
@@ -605,9 +605,6 @@ struct CellInfo : ArchCellInfo
     BelId bel;
     PlaceStrength belStrength = STRENGTH_NONE;
 
-    // cell_port -> bel_pin
-    std::unordered_map<IdString, IdString> pins;
-
     // placement constraints
     CellInfo *constr_parent = nullptr;
     std::vector<CellInfo *> constr_children;
diff --git a/common/pybindings.cc b/common/pybindings.cc
index aacc8d9c..a72da78e 100644
--- a/common/pybindings.cc
+++ b/common/pybindings.cc
@@ -167,8 +167,6 @@ PYBIND11_EMBEDDED_MODULE(MODULE_NAME, m)
                       conv_from_str<BelId>>::def_wrap(ci_cls, "bel");
     readwrite_wrapper<CellInfo &, decltype(&CellInfo::belStrength), &CellInfo::belStrength, pass_through<PlaceStrength>,
                       pass_through<PlaceStrength>>::def_wrap(ci_cls, "belStrength");
-    readonly_wrapper<CellInfo &, decltype(&CellInfo::pins), &CellInfo::pins, wrap_context<IdIdMap &>>::def_wrap(ci_cls,
-                                                                                                                "pins");
 
     fn_wrapper_1a_v<CellInfo &, decltype(&CellInfo::addInput), &CellInfo::addInput, conv_from_str<IdString>>::def_wrap(
             ci_cls, "addInput");
-- 
cgit v1.2.3