From 674cabb6bea05032c8bd7e638684ac7f6e448a6b Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 8 Aug 2018 17:58:25 +0200 Subject: docs: Update Arch API Cell Timing docs Signed-off-by: David Shah --- docs/archapi.md | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'docs/archapi.md') diff --git a/docs/archapi.md b/docs/archapi.md index 222b9f78..3a2b5efb 100644 --- a/docs/archapi.md +++ b/docs/archapi.md @@ -455,13 +455,11 @@ Cell Delay Methods Returns the delay for the specified path through a cell in the `&delay` argument. The method returns false if there is no timing relationship from `fromPort` to `toPort`. -### IdString getPortClock(const CellInfo \*cell, IdString port) const +### TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const -Returns the clock input port for the specified output port. - -### bool isClockPort(const CellInfo \*cell, IdString port) const - -Returns true if the specified port is a clock input. +Return the _timing port class_ of a port. This can be a register or combinational input or output; clock input or +output; general startpoint or endpoint; or a port ignored for timing purposes. For register ports, clockPort is set +to the associated clock port. Placer Methods -------------- -- cgit v1.2.3