From 2eb783d626a9a17baf70d2f7750be3c11623d5bc Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 17 Jul 2018 16:45:39 +0200 Subject: ecp5: Fixing packer bugs Signed-off-by: David Shah --- ecp5/bitstream.cc | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'ecp5/bitstream.cc') diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index e70d6bb2..19ddb9f9 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -214,6 +214,18 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex cc.tiles[tname].add_enum(slice + ".REG1.REGSET", str_or_default(ci->params, ctx->id("REG1_REGSET"), "RESET")); cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, ctx->id("CEMUX"), "1")); + IdString lsrnet; + if (ci->ports.find(ctx->id("LSR")) != ci->ports.end() && ci->ports.at(ctx->id("LSR")).net != nullptr) + lsrnet = ci->ports.at(ctx->id("LSR")).net->name; + if (ctx->getBoundWireNet(ctx->getWireByName( + ctx->id(fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/LSR0")))) == lsrnet) { + cc.tiles[tname].add_enum("LSR0.SRMODE", str_or_default(ci->params, ctx->id("SRMODE"), "LSR_OVER_CE")); + cc.tiles[tname].add_enum("LSR0.LSRMUX", str_or_default(ci->params, ctx->id("LSRMUX"), "LSR")); + } else if (ctx->getBoundWireNet(ctx->getWireByName(ctx->id( + fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/LSR1")))) == lsrnet) { + cc.tiles[tname].add_enum("LSR1.SRMODE", str_or_default(ci->params, ctx->id("SRMODE"), "LSR_OVER_CE")); + cc.tiles[tname].add_enum("LSR1.LSRMUX", str_or_default(ci->params, ctx->id("LSRMUX"), "LSR")); + } // TODO: CLKMUX, CEMUX, carry } else if (ci->type == ctx->id("TRELLIS_IO")) { std::string pio = ctx->locInfo(bel)->bel_data[bel.index].name.get(); -- cgit v1.2.3