From 8604b030088d9b0895a9384b21e37a97741a1ba2 Mon Sep 17 00:00:00 2001 From: gatecat Date: Mon, 12 Jul 2021 11:40:23 +0100 Subject: interchange: Debug IO port validity check failures Signed-off-by: gatecat --- fpga_interchange/arch_pack_io.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'fpga_interchange/arch_pack_io.cc') diff --git a/fpga_interchange/arch_pack_io.cc b/fpga_interchange/arch_pack_io.cc index b018c6bd..38b619a3 100644 --- a/fpga_interchange/arch_pack_io.cc +++ b/fpga_interchange/arch_pack_io.cc @@ -246,7 +246,8 @@ void Arch::pack_ports() if (possible_site_types.empty()) { if (getCtx()->verbose) - log_info("Port '%s' has no possible site types, falling back to all types!\n", port_name.c_str(getCtx())); + log_info("Port '%s' has no possible site types, falling back to all types!\n", + port_name.c_str(getCtx())); possible_site_types = package_pin_site_types; } @@ -316,6 +317,7 @@ void Arch::pack_ports() for (CellInfo *cell : placed_cells) { NPNR_ASSERT(cell->bel != BelId()); if (!isBelLocationValid(cell->bel)) { + explain_bel_status(cell->bel); log_error("Tightly bound BEL %s was not valid!\n", nameOfBel(cell->bel)); } } -- cgit v1.2.3