From a30043c8da1b1cc46a2dcfb90aa3a06d4f4ed4e9 Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Tue, 23 Feb 2021 13:35:45 -0800
Subject: Fix assorted bugs in FPGA interchange.

Fixes:
 - Only use map constant pins during routing, and not during placement.
 - Unmapped cell ports have no BEL pins.
 - Fix SiteRouter congestion not taking into account initial expansion.
 - Fix psuedo-site pip output.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 fpga_interchange/arch_pack_io.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'fpga_interchange/arch_pack_io.cc')

diff --git a/fpga_interchange/arch_pack_io.cc b/fpga_interchange/arch_pack_io.cc
index 6a0ffe0b..06cfa002 100644
--- a/fpga_interchange/arch_pack_io.cc
+++ b/fpga_interchange/arch_pack_io.cc
@@ -243,7 +243,9 @@ void Arch::pack_ports()
 
         for (CellInfo *cell : placed_cells) {
             NPNR_ASSERT(cell->bel != BelId());
-            NPNR_ASSERT(isBelLocationValid(cell->bel));
+            if (!isBelLocationValid(cell->bel)) {
+                log_error("Tightly bound BEL %s was not valid!\n", nameOfBel(cell->bel));
+            }
         }
     }
 }
-- 
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