From 2fc353d5592b0bf9ed8428545bbd6a64312cc16e Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Fri, 19 Feb 2021 16:18:59 -0800 Subject: Add initial logic for handling dedicated interconnect situations. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- fpga_interchange/dedicated_interconnect.h | 129 ++++++++++++++++++++++++++++++ 1 file changed, 129 insertions(+) create mode 100644 fpga_interchange/dedicated_interconnect.h (limited to 'fpga_interchange/dedicated_interconnect.h') diff --git a/fpga_interchange/dedicated_interconnect.h b/fpga_interchange/dedicated_interconnect.h new file mode 100644 index 00000000..5fe61d30 --- /dev/null +++ b/fpga_interchange/dedicated_interconnect.h @@ -0,0 +1,129 @@ +/* + * nextpnr -- Next Generation Place and Route + * + * Copyright (C) 2021 Symbiflow Authors + * + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef NEXTPNR_H +#error Include "dedicated_interconnect.h" via "nextpnr.h" only. +#endif + +NEXTPNR_NAMESPACE_BEGIN + +struct TileTypeBelPin { + int32_t tile_type; + int32_t bel_index; + IdString bel_pin; + + bool operator < (const TileTypeBelPin &other) const { + if(tile_type >= other.tile_type) { + return false; + } + + if(bel_index >= other.bel_index) { + return false; + } + + return bel_pin < other.bel_pin; + } + + bool operator ==(const TileTypeBelPin &other) const { + return tile_type == other.tile_type && bel_index == other.bel_index && bel_pin == other.bel_pin; + } + bool operator !=(const TileTypeBelPin &other) const { + return tile_type != other.tile_type || bel_index != other.bel_index || bel_pin != other.bel_pin; + } +}; + +struct DeltaTileTypeBelPin { + int32_t delta_x; + int32_t delta_y; + TileTypeBelPin type_bel_pin; + + bool operator ==(const DeltaTileTypeBelPin &other) const { + return delta_x == other.delta_x && delta_y == other.delta_y && type_bel_pin == other.type_bel_pin; + } + bool operator !=(const DeltaTileTypeBelPin &other) const { + return delta_x != other.delta_x || delta_y != other.delta_y || type_bel_pin != other.type_bel_pin; + } +}; + +NEXTPNR_NAMESPACE_END + +template <> struct std::hash +{ + std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX TileTypeBelPin &type_bel_pin) const noexcept + { + std::size_t seed = 0; + boost::hash_combine(seed, std::hash()(type_bel_pin.tile_type)); + boost::hash_combine(seed, std::hash()(type_bel_pin.bel_index)); + boost::hash_combine(seed, std::hash()(type_bel_pin.bel_pin)); + return seed; + } +}; + +template <> struct std::hash +{ + std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX DeltaTileTypeBelPin &delta_bel_pin) const noexcept + { + std::size_t seed = 0; + boost::hash_combine(seed, std::hash()(delta_bel_pin.delta_x)); + boost::hash_combine(seed, std::hash()(delta_bel_pin.delta_y)); + boost::hash_combine(seed, std::hash()(delta_bel_pin.type_bel_pin)); + return seed; + } +}; + +NEXTPNR_NAMESPACE_BEGIN + +struct Context; + +// This class models dedicated interconnect present in the given fabric. +// +// Examples of dedicate interconnect: +// - IBUF.O -> ISERDES.I +// - IBUF.O -> IDELAY.I +// - CARRY4.CO[3] -> CARRY4.CIN +// +// Note that CARRY4.CYINIT does not **require** dedicated interconnect, so +// it doesn't qualify. +// +// This class discovers dedicated interconnect by examing the routing graph. +// This discovery make be expensive, and require caching to accelerate +// startup. +struct DedicatedInterconnect { + const Context *ctx; + + std::unordered_map> pins_with_dedicate_interconnect; + + void init(const Context *ctx); + + // Is this BEL placed in a location that is valid based on dedicated + // interconnect? + // + // Note: Only BEL pin sinks are checked. + bool isBelLocationValid(BelId bel, const CellInfo* cell) const; + + void find_dedicated_interconnect(); + void print_dedicated_interconnect() const; + bool check_routing( + BelId src_bel, IdString src_bel_pin, + BelId dst_bel, IdString dst_bel_pin) const; + void expand_bel(BelId bel, IdString pin, WireId wire); +}; + +NEXTPNR_NAMESPACE_END -- cgit v1.2.3 From 184665652eaf351bf9337b524c5d82a50ce54041 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Mon, 22 Feb 2021 09:13:44 -0800 Subject: Finish dedicated interconnect implementation. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- fpga_interchange/dedicated_interconnect.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'fpga_interchange/dedicated_interconnect.h') diff --git a/fpga_interchange/dedicated_interconnect.h b/fpga_interchange/dedicated_interconnect.h index 5fe61d30..d603039e 100644 --- a/fpga_interchange/dedicated_interconnect.h +++ b/fpga_interchange/dedicated_interconnect.h @@ -108,7 +108,8 @@ struct Context; struct DedicatedInterconnect { const Context *ctx; - std::unordered_map> pins_with_dedicate_interconnect; + std::unordered_map> sinks; + std::unordered_map> sources; void init(const Context *ctx); @@ -123,7 +124,13 @@ struct DedicatedInterconnect { bool check_routing( BelId src_bel, IdString src_bel_pin, BelId dst_bel, IdString dst_bel_pin) const; - void expand_bel(BelId bel, IdString pin, WireId wire); + void expand_sink_bel(BelId bel, IdString pin, WireId wire); + void expand_source_bel(BelId bel, IdString pin, WireId wire); + + bool is_driver_on_net_valid(BelId driver_bel, + const CellInfo* cell, IdString driver_port, NetInfo *net) const; + bool is_sink_on_net_valid(BelId bel, const CellInfo* cell, + IdString port_name, NetInfo *net) const; }; NEXTPNR_NAMESPACE_END -- cgit v1.2.3 From a30043c8da1b1cc46a2dcfb90aa3a06d4f4ed4e9 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Tue, 23 Feb 2021 13:35:45 -0800 Subject: Fix assorted bugs in FPGA interchange. Fixes: - Only use map constant pins during routing, and not during placement. - Unmapped cell ports have no BEL pins. - Fix SiteRouter congestion not taking into account initial expansion. - Fix psuedo-site pip output. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- fpga_interchange/dedicated_interconnect.h | 40 +++++++++++++++++-------------- 1 file changed, 22 insertions(+), 18 deletions(-) (limited to 'fpga_interchange/dedicated_interconnect.h') diff --git a/fpga_interchange/dedicated_interconnect.h b/fpga_interchange/dedicated_interconnect.h index d603039e..66e1d41b 100644 --- a/fpga_interchange/dedicated_interconnect.h +++ b/fpga_interchange/dedicated_interconnect.h @@ -24,40 +24,47 @@ NEXTPNR_NAMESPACE_BEGIN -struct TileTypeBelPin { +struct TileTypeBelPin +{ int32_t tile_type; int32_t bel_index; IdString bel_pin; - bool operator < (const TileTypeBelPin &other) const { - if(tile_type >= other.tile_type) { + bool operator<(const TileTypeBelPin &other) const + { + if (tile_type >= other.tile_type) { return false; } - if(bel_index >= other.bel_index) { + if (bel_index >= other.bel_index) { return false; } return bel_pin < other.bel_pin; } - bool operator ==(const TileTypeBelPin &other) const { + bool operator==(const TileTypeBelPin &other) const + { return tile_type == other.tile_type && bel_index == other.bel_index && bel_pin == other.bel_pin; } - bool operator !=(const TileTypeBelPin &other) const { + bool operator!=(const TileTypeBelPin &other) const + { return tile_type != other.tile_type || bel_index != other.bel_index || bel_pin != other.bel_pin; } }; -struct DeltaTileTypeBelPin { +struct DeltaTileTypeBelPin +{ int32_t delta_x; int32_t delta_y; TileTypeBelPin type_bel_pin; - bool operator ==(const DeltaTileTypeBelPin &other) const { + bool operator==(const DeltaTileTypeBelPin &other) const + { return delta_x == other.delta_x && delta_y == other.delta_y && type_bel_pin == other.type_bel_pin; } - bool operator !=(const DeltaTileTypeBelPin &other) const { + bool operator!=(const DeltaTileTypeBelPin &other) const + { return delta_x != other.delta_x || delta_y != other.delta_y || type_bel_pin != other.type_bel_pin; } }; @@ -105,7 +112,8 @@ struct Context; // This class discovers dedicated interconnect by examing the routing graph. // This discovery make be expensive, and require caching to accelerate // startup. -struct DedicatedInterconnect { +struct DedicatedInterconnect +{ const Context *ctx; std::unordered_map> sinks; @@ -117,20 +125,16 @@ struct DedicatedInterconnect { // interconnect? // // Note: Only BEL pin sinks are checked. - bool isBelLocationValid(BelId bel, const CellInfo* cell) const; + bool isBelLocationValid(BelId bel, const CellInfo *cell) const; void find_dedicated_interconnect(); void print_dedicated_interconnect() const; - bool check_routing( - BelId src_bel, IdString src_bel_pin, - BelId dst_bel, IdString dst_bel_pin) const; + bool check_routing(BelId src_bel, IdString src_bel_pin, BelId dst_bel, IdString dst_bel_pin) const; void expand_sink_bel(BelId bel, IdString pin, WireId wire); void expand_source_bel(BelId bel, IdString pin, WireId wire); - bool is_driver_on_net_valid(BelId driver_bel, - const CellInfo* cell, IdString driver_port, NetInfo *net) const; - bool is_sink_on_net_valid(BelId bel, const CellInfo* cell, - IdString port_name, NetInfo *net) const; + bool is_driver_on_net_valid(BelId driver_bel, const CellInfo *cell, IdString driver_port, NetInfo *net) const; + bool is_sink_on_net_valid(BelId bel, const CellInfo *cell, IdString port_name, NetInfo *net) const; }; NEXTPNR_NAMESPACE_END -- cgit v1.2.3