From cf554f9338db84fa0d12afd83e10f7791e62efa1 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Thu, 18 Feb 2021 16:51:05 -0800 Subject: Add constant network test case. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- fpga_interchange/examples/const_wire/Makefile | 8 ++++++++ fpga_interchange/examples/const_wire/run.tcl | 14 ++++++++++++++ fpga_interchange/examples/const_wire/wire.v | 6 ++++++ fpga_interchange/examples/const_wire/wire.xdc | 5 +++++ 4 files changed, 33 insertions(+) create mode 100644 fpga_interchange/examples/const_wire/Makefile create mode 100644 fpga_interchange/examples/const_wire/run.tcl create mode 100644 fpga_interchange/examples/const_wire/wire.v create mode 100644 fpga_interchange/examples/const_wire/wire.xdc (limited to 'fpga_interchange/examples/const_wire') diff --git a/fpga_interchange/examples/const_wire/Makefile b/fpga_interchange/examples/const_wire/Makefile new file mode 100644 index 00000000..49194f53 --- /dev/null +++ b/fpga_interchange/examples/const_wire/Makefile @@ -0,0 +1,8 @@ +DESIGN := wire +DESIGN_TOP := top +PACKAGE := csg324 + +include ../template.mk + +build/wire.json: wire.v | build + yosys -c run.tcl diff --git a/fpga_interchange/examples/const_wire/run.tcl b/fpga_interchange/examples/const_wire/run.tcl new file mode 100644 index 00000000..9127be20 --- /dev/null +++ b/fpga_interchange/examples/const_wire/run.tcl @@ -0,0 +1,14 @@ +yosys -import + +read_verilog wire.v + +synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json build/wire.json diff --git a/fpga_interchange/examples/const_wire/wire.v b/fpga_interchange/examples/const_wire/wire.v new file mode 100644 index 00000000..7905c92e --- /dev/null +++ b/fpga_interchange/examples/const_wire/wire.v @@ -0,0 +1,6 @@ +module top(output o, output o2); + +assign o = 1'b0; +assign o2 = 1'b1; + +endmodule diff --git a/fpga_interchange/examples/const_wire/wire.xdc b/fpga_interchange/examples/const_wire/wire.xdc new file mode 100644 index 00000000..beab748e --- /dev/null +++ b/fpga_interchange/examples/const_wire/wire.xdc @@ -0,0 +1,5 @@ +set_property PACKAGE_PIN N15 [get_ports o] +set_property PACKAGE_PIN N16 [get_ports o2] + +set_property IOSTANDARD LVCMOS33 [get_ports o] +set_property IOSTANDARD LVCMOS33 [get_ports o2] -- cgit v1.2.3 From 15459cae91276f956d2a4734f42162d6afaf1128 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Thu, 18 Feb 2021 16:51:36 -0800 Subject: Initial working constant network support! Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- fpga_interchange/examples/const_wire/wire.v | 4 +++- fpga_interchange/examples/const_wire/wire.xdc | 4 ++++ 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'fpga_interchange/examples/const_wire') diff --git a/fpga_interchange/examples/const_wire/wire.v b/fpga_interchange/examples/const_wire/wire.v index 7905c92e..5b1ab692 100644 --- a/fpga_interchange/examples/const_wire/wire.v +++ b/fpga_interchange/examples/const_wire/wire.v @@ -1,6 +1,8 @@ -module top(output o, output o2); +module top(output o, output o2, output o3, output o4); assign o = 1'b0; assign o2 = 1'b1; +assign o3 = 1'b0; +assign o4 = 1'b1; endmodule diff --git a/fpga_interchange/examples/const_wire/wire.xdc b/fpga_interchange/examples/const_wire/wire.xdc index beab748e..0d96fc45 100644 --- a/fpga_interchange/examples/const_wire/wire.xdc +++ b/fpga_interchange/examples/const_wire/wire.xdc @@ -1,5 +1,9 @@ set_property PACKAGE_PIN N15 [get_ports o] set_property PACKAGE_PIN N16 [get_ports o2] +set_property PACKAGE_PIN P17 [get_ports o3] +set_property PACKAGE_PIN R17 [get_ports o4] set_property IOSTANDARD LVCMOS33 [get_ports o] set_property IOSTANDARD LVCMOS33 [get_ports o2] +set_property IOSTANDARD LVCMOS33 [get_ports o3] +set_property IOSTANDARD LVCMOS33 [get_ports o4] -- cgit v1.2.3