From bd2da27e4e35e92ad91145921cf9c7d2c490a9df Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Fri, 12 Mar 2021 19:03:02 +0100 Subject: fpga_interchange: tests: added comment and fixed XDC Signed-off-by: Alessandro Comodi --- fpga_interchange/examples/tests/wire/CMakeLists.txt | 8 ++++---- fpga_interchange/examples/tests/wire/wire.xdc | 5 ----- fpga_interchange/examples/tests/wire/wire_arty.xdc | 5 +++++ fpga_interchange/examples/tests/wire/wire_basys3.xdc | 5 +++++ 4 files changed, 14 insertions(+), 9 deletions(-) delete mode 100644 fpga_interchange/examples/tests/wire/wire.xdc create mode 100644 fpga_interchange/examples/tests/wire/wire_arty.xdc create mode 100644 fpga_interchange/examples/tests/wire/wire_basys3.xdc (limited to 'fpga_interchange/examples/tests/wire') diff --git a/fpga_interchange/examples/tests/wire/CMakeLists.txt b/fpga_interchange/examples/tests/wire/CMakeLists.txt index 1d3b36ac..9af3f0db 100644 --- a/fpga_interchange/examples/tests/wire/CMakeLists.txt +++ b/fpga_interchange/examples/tests/wire/CMakeLists.txt @@ -1,17 +1,17 @@ add_interchange_test( name wire_basys3 - device xc7a50t + device xc7a35t package cpg236 tcl run.tcl - xdc wire.xdc + xdc wire_basys3.xdc sources wire.v ) add_interchange_test( name wire_arty - device xc7a50t + device xc7a35t package csg324 tcl run.tcl - xdc wire.xdc + xdc wire_arty.xdc sources wire.v ) diff --git a/fpga_interchange/examples/tests/wire/wire.xdc b/fpga_interchange/examples/tests/wire/wire.xdc deleted file mode 100644 index c923f0fc..00000000 --- a/fpga_interchange/examples/tests/wire/wire.xdc +++ /dev/null @@ -1,5 +0,0 @@ -set_property PACKAGE_PIN N16 [get_ports i] -set_property PACKAGE_PIN N15 [get_ports o] - -set_property IOSTANDARD LVCMOS33 [get_ports i] -set_property IOSTANDARD LVCMOS33 [get_ports o] diff --git a/fpga_interchange/examples/tests/wire/wire_arty.xdc b/fpga_interchange/examples/tests/wire/wire_arty.xdc new file mode 100644 index 00000000..c923f0fc --- /dev/null +++ b/fpga_interchange/examples/tests/wire/wire_arty.xdc @@ -0,0 +1,5 @@ +set_property PACKAGE_PIN N16 [get_ports i] +set_property PACKAGE_PIN N15 [get_ports o] + +set_property IOSTANDARD LVCMOS33 [get_ports i] +set_property IOSTANDARD LVCMOS33 [get_ports o] diff --git a/fpga_interchange/examples/tests/wire/wire_basys3.xdc b/fpga_interchange/examples/tests/wire/wire_basys3.xdc new file mode 100644 index 00000000..317d5acc --- /dev/null +++ b/fpga_interchange/examples/tests/wire/wire_basys3.xdc @@ -0,0 +1,5 @@ +set_property PACKAGE_PIN V17 [get_ports i] +set_property PACKAGE_PIN U16 [get_ports o] + +set_property IOSTANDARD LVCMOS33 [get_ports i] +set_property IOSTANDARD LVCMOS33 [get_ports o] -- cgit v1.2.3