From 49caad0b7b22f44039cdaaefa352fd6fea2ecf30 Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Tue, 6 Apr 2021 10:48:04 +0100
Subject: interchange/nexus: Add counter example

Signed-off-by: gatecat <gatecat@ds0.me>
---
 fpga_interchange/examples/tests/counter/CMakeLists.txt | 14 ++++++++++++--
 fpga_interchange/examples/tests/counter/lifcl17.xdc    | 14 ++++++++++++++
 fpga_interchange/examples/tests/counter/run.tcl        | 15 ---------------
 fpga_interchange/examples/tests/counter/run_nexus.tcl  | 15 +++++++++++++++
 fpga_interchange/examples/tests/counter/run_xilinx.tcl | 15 +++++++++++++++
 5 files changed, 56 insertions(+), 17 deletions(-)
 create mode 100644 fpga_interchange/examples/tests/counter/lifcl17.xdc
 delete mode 100644 fpga_interchange/examples/tests/counter/run.tcl
 create mode 100644 fpga_interchange/examples/tests/counter/run_nexus.tcl
 create mode 100644 fpga_interchange/examples/tests/counter/run_xilinx.tcl

(limited to 'fpga_interchange/examples/tests')

diff --git a/fpga_interchange/examples/tests/counter/CMakeLists.txt b/fpga_interchange/examples/tests/counter/CMakeLists.txt
index 38c104ff..91929f93 100644
--- a/fpga_interchange/examples/tests/counter/CMakeLists.txt
+++ b/fpga_interchange/examples/tests/counter/CMakeLists.txt
@@ -2,8 +2,18 @@ add_interchange_group_test(
     name counter
     family ${family}
     board_list basys3 arty35t arty100t zybo
-    tcl run.tcl
+    tcl run_xilinx.tcl
     sources counter.v
-    techmap ../../remap.v
+    techmap ../../remap_xilinx.v
     output_fasm
 )
+
+add_interchange_group_test(
+    name counter
+    family ${family}
+    board_list lifcl17
+    tcl run_nexus.tcl
+    sources counter.v
+    techmap ../../remap_nexus.v
+    skip_dcp
+)
diff --git a/fpga_interchange/examples/tests/counter/lifcl17.xdc b/fpga_interchange/examples/tests/counter/lifcl17.xdc
new file mode 100644
index 00000000..2031964e
--- /dev/null
+++ b/fpga_interchange/examples/tests/counter/lifcl17.xdc
@@ -0,0 +1,14 @@
+## lifcl17 pins for testing based on breakout board
+set_property PACKAGE_PIN 55 [get_ports clk]
+set_property PACKAGE_PIN 57 [get_ports rst]
+set_property PACKAGE_PIN 56 [get_ports io_led[4]]
+set_property PACKAGE_PIN 59 [get_ports io_led[5]]
+set_property PACKAGE_PIN 60 [get_ports io_led[6]]
+set_property PACKAGE_PIN 61 [get_ports io_led[7]]
+
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports rst]
+set_property IOSTANDARD LVCMOS33 [get_ports io_led[4]]
+set_property IOSTANDARD LVCMOS33 [get_ports io_led[5]]
+set_property IOSTANDARD LVCMOS33 [get_ports io_led[6]]
+set_property IOSTANDARD LVCMOS33 [get_ports io_led[7]]
diff --git a/fpga_interchange/examples/tests/counter/run.tcl b/fpga_interchange/examples/tests/counter/run.tcl
deleted file mode 100644
index ffea3b2e..00000000
--- a/fpga_interchange/examples/tests/counter/run.tcl
+++ /dev/null
@@ -1,15 +0,0 @@
-yosys -import
-
-read_verilog $::env(SOURCES)
-
-synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
-techmap -map $::env(TECHMAP)
-
-# opt_expr -undriven makes sure all nets are driven, if only by the $undef
-# net.
-opt_expr -undriven
-opt_clean
-
-setundef -zero -params
-
-write_json $::env(OUT_JSON)
diff --git a/fpga_interchange/examples/tests/counter/run_nexus.tcl b/fpga_interchange/examples/tests/counter/run_nexus.tcl
new file mode 100644
index 00000000..80150571
--- /dev/null
+++ b/fpga_interchange/examples/tests/counter/run_nexus.tcl
@@ -0,0 +1,15 @@
+yosys -import
+
+read_verilog $::env(SOURCES)
+
+synth_nexus -nolutram -nowidelut -nobram -noccu2 -nodsp
+techmap -max_iter 1 -map $::env(TECHMAP)
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json $::env(OUT_JSON)
diff --git a/fpga_interchange/examples/tests/counter/run_xilinx.tcl b/fpga_interchange/examples/tests/counter/run_xilinx.tcl
new file mode 100644
index 00000000..ffea3b2e
--- /dev/null
+++ b/fpga_interchange/examples/tests/counter/run_xilinx.tcl
@@ -0,0 +1,15 @@
+yosys -import
+
+read_verilog $::env(SOURCES)
+
+synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
+techmap -map $::env(TECHMAP)
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json $::env(OUT_JSON)
-- 
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