From bae83857a3bfe533a519c750f611e0e73c7ce4ef Mon Sep 17 00:00:00 2001 From: gatecat Date: Thu, 13 May 2021 11:31:03 +0100 Subject: interchange: Add macro parameter mapping Signed-off-by: gatecat --- fpga_interchange/examples/tests/lutram/lutram.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'fpga_interchange/examples/tests') diff --git a/fpga_interchange/examples/tests/lutram/lutram.v b/fpga_interchange/examples/tests/lutram/lutram.v index be5728f8..f38197d4 100644 --- a/fpga_interchange/examples/tests/lutram/lutram.v +++ b/fpga_interchange/examples/tests/lutram/lutram.v @@ -7,7 +7,9 @@ module top ( input wire [15:0] sw, output wire [15:0] led ); - RAM128X1D ram_i ( + RAM128X1D #( + .INIT(128'hFFEEDDCCBBAA99887766554433221100) + ) ram_i ( .WCLK(clk), .A(sw[6:0]), .DPRA(sw[13:7]), -- cgit v1.2.3