From 104536b7aae5970ae1d1e95394f26fbf04603d12 Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Wed, 2 Jun 2021 09:49:30 +0200 Subject: interchange: add support for generating BEL clusters Clustering greatly helps the placer to identify and pack together specific cells at the same site (e.g. LUT+FF), or cells that are chained through dedicated interconnections (e.g. CARRY CHAINS) Signed-off-by: Alessandro Comodi --- fpga_interchange/fpga_interchange.cpp | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'fpga_interchange/fpga_interchange.cpp') diff --git a/fpga_interchange/fpga_interchange.cpp b/fpga_interchange/fpga_interchange.cpp index 1d08b128..ac2a7e96 100644 --- a/fpga_interchange/fpga_interchange.cpp +++ b/fpga_interchange/fpga_interchange.cpp @@ -539,10 +539,14 @@ void FpgaInterchange::write_physical_netlist(const Context * ctx, const std::str auto net_iter = nets.begin(); for(auto & net_pair : ctx->nets) { auto &net = *net_pair.second; - auto net_out = *net_iter++; const CellInfo *driver_cell = net.driver.cell; + if (driver_cell == nullptr) + continue; + + auto net_out = *net_iter++; + // Handle GND and VCC nets. if(driver_cell->bel == ctx->get_gnd_bel()) { IdString gnd_net_name(ctx->chip_info->constants->gnd_net_name); -- cgit v1.2.3