From d52516756cf32ecb53b75e8a6f032ebeeb427a71 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Fri, 9 Jul 2021 15:40:06 +0200 Subject: Working site LUT mapping cache Signed-off-by: Maciej Kurc --- fpga_interchange/luts.cc | 107 ++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 92 insertions(+), 15 deletions(-) (limited to 'fpga_interchange/luts.cc') diff --git a/fpga_interchange/luts.cc b/fpga_interchange/luts.cc index 0156d379..2ac3b6da 100644 --- a/fpga_interchange/luts.cc +++ b/fpga_interchange/luts.cc @@ -22,6 +22,8 @@ #include "log.h" #include "nextpnr.h" +#include "site_lut_mapping_cache.h" + //#define DEBUG_LUT_ROTATION NEXTPNR_NAMESPACE_BEGIN @@ -253,7 +255,7 @@ uint32_t LutMapper::check_wires(const std::vector> &bel_to_ return vcc_mask; } -bool LutMapper::remap_luts(const Context *ctx, pool *blocked_luts) +bool LutMapper::remap_luts(const Context *ctx, SiteLutMappingResult* lut_mapping, pool *blocked_luts) { dict lut_pin_map; std::vector lut_bels; @@ -377,6 +379,94 @@ bool LutMapper::remap_luts(const Context *ctx, pool %s", ctx->nameOfBel(cell->bel), cell->name.c_str(ctx)); + } + log("\n"); +#endif + } + + // Fill in the LUT mapping result + + // Push new cell -> BEL pin maps out to cells now that equations have been + // verified! + lut_mapping->cells.reserve(cells.size()); + for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) { + CellInfo *cellInfo = cells[cell_idx]; + auto &lutBel = *lut_bels[cell_idx]; + + // Add the cell data + SiteLutMappingResult::Cell cell; + cell.belIndex = cellInfo->bel.index; + + // Cell to BEL pin map + for (size_t pin_idx = 0; pin_idx < cellInfo->lut_cell.pins.size(); ++pin_idx) { + IdString cellPin = cellInfo->lut_cell.pins[pin_idx]; + IdString belPin = lutBel.pins[cell_to_bel_pin_remaps[cell_idx][pin_idx]]; + cell.belPins[cellPin] = belPin; + } + + cell.lutCell.vcc_pins.clear(); + + // All LUT inputs used + if (cells.size() == element.lut_bels.size()) { + for (size_t bel_pin_idx = 0; bel_pin_idx < lutBel.pins.size(); ++bel_pin_idx) { + if ((used_pins & (1 << bel_pin_idx)) == 0) { + NPNR_ASSERT(bel_to_cell_pin_remaps[cell_idx][bel_pin_idx] == -1); + cell.lutCell.vcc_pins.emplace(lutBel.pins.at(bel_pin_idx)); + } + } + } + // Only some LUT inputs used + else { + for (size_t bel_pin_idx = 0; bel_pin_idx < lutBel.pins.size(); ++bel_pin_idx) { + if ((vcc_pins & (1 << bel_pin_idx)) != 0) { + NPNR_ASSERT(bel_to_cell_pin_remaps[cell_idx][bel_pin_idx] == -1); + auto pin = lutBel.pins.at(bel_pin_idx); + cell.lutCell.vcc_pins.emplace(pin); + } + } + } + + lut_mapping->cells.push_back(cell); + } + +/* +#ifdef DEBUG_LUT_ROTATION + log_info("Final mapping:\n"); + for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) { + CellInfo *cell = cells[cell_idx]; + for (auto &cell_pin_pair : cell->cell_bel_pins) { + log_info("%s %s %s =>", cell->type.c_str(ctx), cell->name.c_str(ctx), cell_pin_pair.first.c_str(ctx)); + for (auto bel_pin : cell_pin_pair.second) { + log(" %s", bel_pin.c_str(ctx)); + } + log("\n"); + } + } +#endif +*/ + + + + +/* + // Push new cell -> BEL pin maps out to cells now that equations have been // verified! for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) { @@ -434,20 +524,7 @@ bool LutMapper::remap_luts(const Context *ctx, poolcell_bel_pins) { - log_info("%s %s %s =>", cell->type.c_str(ctx), cell->name.c_str(ctx), cell_pin_pair.first.c_str(ctx)); - for (auto bel_pin : cell_pin_pair.second) { - log(" %s", bel_pin.c_str(ctx)); - } - log("\n"); - } - } -#endif +*/ return true; } -- cgit v1.2.3 From 0336f55b16373874cf4ac5661d9724d0a358454c Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Fri, 16 Jul 2021 13:55:19 +0200 Subject: LUT mapping ceche optimizations 2 Signed-off-by: Maciej Kurc --- fpga_interchange/luts.cc | 80 ------------------------------------------------ 1 file changed, 80 deletions(-) (limited to 'fpga_interchange/luts.cc') diff --git a/fpga_interchange/luts.cc b/fpga_interchange/luts.cc index 2ac3b6da..9c68739e 100644 --- a/fpga_interchange/luts.cc +++ b/fpga_interchange/luts.cc @@ -446,86 +446,6 @@ bool LutMapper::remap_luts(const Context *ctx, SiteLutMappingResult* lut_mapping lut_mapping->cells.push_back(cell); } -/* -#ifdef DEBUG_LUT_ROTATION - log_info("Final mapping:\n"); - for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) { - CellInfo *cell = cells[cell_idx]; - for (auto &cell_pin_pair : cell->cell_bel_pins) { - log_info("%s %s %s =>", cell->type.c_str(ctx), cell->name.c_str(ctx), cell_pin_pair.first.c_str(ctx)); - for (auto bel_pin : cell_pin_pair.second) { - log(" %s", bel_pin.c_str(ctx)); - } - log("\n"); - } - } -#endif -*/ - - - - -/* - - // Push new cell -> BEL pin maps out to cells now that equations have been - // verified! - for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) { - CellInfo *cell = cells[cell_idx]; - auto &lut_bel = *lut_bels[cell_idx]; - - for (size_t pin_idx = 0; pin_idx < cell->lut_cell.pins.size(); ++pin_idx) { - auto &bel_pins = cell->cell_bel_pins[cell->lut_cell.pins[pin_idx]]; - bel_pins.clear(); - bel_pins.push_back(lut_bel.pins[cell_to_bel_pin_remaps[cell_idx][pin_idx]]); - } - } - - if (cells.size() == element.lut_bels.size()) { - for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) { - CellInfo *cell = cells[cell_idx]; - auto &lut_bel = *lut_bels[cell_idx]; - cell->lut_cell.vcc_pins.clear(); - for (size_t bel_pin_idx = 0; bel_pin_idx < lut_bel.pins.size(); ++bel_pin_idx) { - if ((used_pins & (1 << bel_pin_idx)) == 0) { - NPNR_ASSERT(bel_to_cell_pin_remaps[cell_idx][bel_pin_idx] == -1); - cell->lut_cell.vcc_pins.emplace(lut_bel.pins.at(bel_pin_idx)); - } - } - } - } else { - // Look to see if wires can be run from element inputs to unused - // outputs. If not, block the BEL pin by tying to VCC. - // - // FIXME: The assumption is that unused pins are tied VCC. - // This is not generally true. - // - // Use Arch::prefered_constant_net_type to determine what - // constant net should be used for unused pins. - uint32_t vcc_pins = check_wires(bel_to_cell_pin_remaps, lut_bels, used_pins, blocked_luts); -#if defined(DEBUG_LUT_ROTATION) - log_info("vcc_pins = 0x%x", vcc_pins); - for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) { - CellInfo *cell = cells[cell_idx]; - log(", %s => %s", ctx->nameOfBel(cell->bel), cell->name.c_str(ctx)); - } - log("\n"); -#endif - - for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) { - CellInfo *cell = cells[cell_idx]; - auto &lut_bel = *lut_bels[cell_idx]; - cell->lut_cell.vcc_pins.clear(); - for (size_t bel_pin_idx = 0; bel_pin_idx < lut_bel.pins.size(); ++bel_pin_idx) { - if ((vcc_pins & (1 << bel_pin_idx)) != 0) { - NPNR_ASSERT(bel_to_cell_pin_remaps[cell_idx][bel_pin_idx] == -1); - auto pin = lut_bel.pins.at(bel_pin_idx); - cell->lut_cell.vcc_pins.emplace(pin); - } - } - } - } -*/ - return true; } -- cgit v1.2.3 From 8fc16a57c9dee5e7e0f83752a62612f70f18a38e Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Fri, 16 Jul 2021 16:01:21 +0200 Subject: Added more code comments, formatted the code Signed-off-by: Maciej Kurc --- fpga_interchange/luts.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'fpga_interchange/luts.cc') diff --git a/fpga_interchange/luts.cc b/fpga_interchange/luts.cc index 9c68739e..d9e17ca9 100644 --- a/fpga_interchange/luts.cc +++ b/fpga_interchange/luts.cc @@ -255,7 +255,8 @@ uint32_t LutMapper::check_wires(const std::vector> &bel_to_ return vcc_mask; } -bool LutMapper::remap_luts(const Context *ctx, SiteLutMappingResult* lut_mapping, pool *blocked_luts) +bool LutMapper::remap_luts(const Context *ctx, SiteLutMappingResult *lut_mapping, + pool *blocked_luts) { dict lut_pin_map; std::vector lut_bels; @@ -417,7 +418,7 @@ bool LutMapper::remap_luts(const Context *ctx, SiteLutMappingResult* lut_mapping // Cell to BEL pin map for (size_t pin_idx = 0; pin_idx < cellInfo->lut_cell.pins.size(); ++pin_idx) { IdString cellPin = cellInfo->lut_cell.pins[pin_idx]; - IdString belPin = lutBel.pins[cell_to_bel_pin_remaps[cell_idx][pin_idx]]; + IdString belPin = lutBel.pins[cell_to_bel_pin_remaps[cell_idx][pin_idx]]; cell.belPins[cellPin] = belPin; } -- cgit v1.2.3