From 2fc353d5592b0bf9ed8428545bbd6a64312cc16e Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Fri, 19 Feb 2021 16:18:59 -0800 Subject: Add initial logic for handling dedicated interconnect situations. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- fpga_interchange/main.cc | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'fpga_interchange/main.cc') diff --git a/fpga_interchange/main.cc b/fpga_interchange/main.cc index 5a49cbdc..958f1d95 100644 --- a/fpga_interchange/main.cc +++ b/fpga_interchange/main.cc @@ -70,6 +70,7 @@ void FpgaInterchangeCommandHandler::customBitstream(Context *ctx) std::unique_ptr FpgaInterchangeCommandHandler::createContext(std::unordered_map &values) { auto start = std::chrono::high_resolution_clock::now(); + ArchArgs chipArgs; if (!vm.count("chipdb")) { log_error("chip database binary must be provided\n"); @@ -81,6 +82,16 @@ std::unique_ptr FpgaInterchangeCommandHandler::createContext(std::unord auto ctx = std::unique_ptr(new Context(chipArgs)); + if (vm.count("verbose")) { + ctx->verbose = true; + } + if (vm.count("debug")) { + ctx->verbose = true; + ctx->debug = true; + } + + ctx->init(); + if (vm.count("netlist")) { ctx->read_logical_netlist(vm["netlist"].as()); } -- cgit v1.2.3