From 4812092cdbda0da395b8df55eaa65c29ec421b8b Mon Sep 17 00:00:00 2001
From: Alessandro Comodi <acomodi@antmicro.com>
Date: Fri, 19 Mar 2021 17:38:45 +0100
Subject: fpga_interchange: add test data for new architectures

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
---
 .../examples/devices/xc7a100t/test_data.yaml       | 36 ++++++++++++++++++++++
 .../examples/devices/xc7a200t/test_data.yaml       | 36 ++++++++++++++++++++++
 .../examples/devices/xc7z010/test_data.yaml        | 36 ++++++++++++++++++++++
 3 files changed, 108 insertions(+)
 create mode 100644 fpga_interchange/examples/devices/xc7a100t/test_data.yaml
 create mode 100644 fpga_interchange/examples/devices/xc7a200t/test_data.yaml
 create mode 100644 fpga_interchange/examples/devices/xc7z010/test_data.yaml

(limited to 'fpga_interchange')

diff --git a/fpga_interchange/examples/devices/xc7a100t/test_data.yaml b/fpga_interchange/examples/devices/xc7a100t/test_data.yaml
new file mode 100644
index 00000000..268d180a
--- /dev/null
+++ b/fpga_interchange/examples/devices/xc7a100t/test_data.yaml
@@ -0,0 +1,36 @@
+pip_test:
+    - src_wire: CLBLM_R_X11Y93/CLBLM_L_D3
+      dst_wire: SLICE_X15Y93.SLICEL/D3
+pip_chain_test:
+    - wires:
+        - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+        - $CONSTANTS_X0Y0/$GND_NODE
+        - TIEOFF_X3Y145.TIEOFF/$GND_SITE_WIRE
+        - TIEOFF_X3Y145.TIEOFF/HARD0GND_HARD0
+        - INT_R_X3Y145/GND_WIRE
+    - wires:
+        - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
+        - $CONSTANTS_X0Y0/$VCC_NODE
+        - TIEOFF_X3Y145.TIEOFF/$VCC_SITE_WIRE
+        - TIEOFF_X3Y145.TIEOFF/HARD1VCC_HARD1
+        - INT_R_X3Y145/VCC_WIRE
+    - wires:
+        - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
+        - $CONSTANTS_X0Y0/$VCC_NODE
+        - SLICE_X3Y145.SLICEL/$VCC_SITE_WIRE
+        - SLICE_X3Y145.SLICEL/CEUSEDVCC_HARD1
+    - wires:
+        - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+        - $CONSTANTS_X0Y0/$GND_NODE
+        - SLICE_X3Y145.SLICEL/$GND_SITE_WIRE
+        - SLICE_X3Y145.SLICEL/SRUSEDGND_HARD0
+bel_pin_test:
+    - bel: SLICE_X15Y93.SLICEL/D6LUT
+      pin: A3
+      wire: SLICE_X15Y93.SLICEL/D3
+    - bel: $CONSTANTS_X0Y0.$CONSTANTS/GND
+      pin: G
+      wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+    - bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC
+      pin: P
+      wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
diff --git a/fpga_interchange/examples/devices/xc7a200t/test_data.yaml b/fpga_interchange/examples/devices/xc7a200t/test_data.yaml
new file mode 100644
index 00000000..268d180a
--- /dev/null
+++ b/fpga_interchange/examples/devices/xc7a200t/test_data.yaml
@@ -0,0 +1,36 @@
+pip_test:
+    - src_wire: CLBLM_R_X11Y93/CLBLM_L_D3
+      dst_wire: SLICE_X15Y93.SLICEL/D3
+pip_chain_test:
+    - wires:
+        - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+        - $CONSTANTS_X0Y0/$GND_NODE
+        - TIEOFF_X3Y145.TIEOFF/$GND_SITE_WIRE
+        - TIEOFF_X3Y145.TIEOFF/HARD0GND_HARD0
+        - INT_R_X3Y145/GND_WIRE
+    - wires:
+        - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
+        - $CONSTANTS_X0Y0/$VCC_NODE
+        - TIEOFF_X3Y145.TIEOFF/$VCC_SITE_WIRE
+        - TIEOFF_X3Y145.TIEOFF/HARD1VCC_HARD1
+        - INT_R_X3Y145/VCC_WIRE
+    - wires:
+        - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
+        - $CONSTANTS_X0Y0/$VCC_NODE
+        - SLICE_X3Y145.SLICEL/$VCC_SITE_WIRE
+        - SLICE_X3Y145.SLICEL/CEUSEDVCC_HARD1
+    - wires:
+        - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+        - $CONSTANTS_X0Y0/$GND_NODE
+        - SLICE_X3Y145.SLICEL/$GND_SITE_WIRE
+        - SLICE_X3Y145.SLICEL/SRUSEDGND_HARD0
+bel_pin_test:
+    - bel: SLICE_X15Y93.SLICEL/D6LUT
+      pin: A3
+      wire: SLICE_X15Y93.SLICEL/D3
+    - bel: $CONSTANTS_X0Y0.$CONSTANTS/GND
+      pin: G
+      wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+    - bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC
+      pin: P
+      wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
diff --git a/fpga_interchange/examples/devices/xc7z010/test_data.yaml b/fpga_interchange/examples/devices/xc7z010/test_data.yaml
new file mode 100644
index 00000000..dbc95845
--- /dev/null
+++ b/fpga_interchange/examples/devices/xc7z010/test_data.yaml
@@ -0,0 +1,36 @@
+pip_test:
+    - src_wire: CLBLM_L_X8Y69/CLBLM_L_D3
+      dst_wire: SLICE_X11Y69.SLICEL/D3
+pip_chain_test:
+    - wires:
+        - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+        - $CONSTANTS_X0Y0/$GND_NODE
+        - TIEOFF_X9Y69.TIEOFF/$GND_SITE_WIRE
+        - TIEOFF_X9Y69.TIEOFF/HARD0GND_HARD0
+        - INT_L_X8Y69/GND_WIRE
+    - wires:
+        - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
+        - $CONSTANTS_X0Y0/$VCC_NODE
+        - TIEOFF_X9Y69.TIEOFF/$VCC_SITE_WIRE
+        - TIEOFF_X9Y69.TIEOFF/HARD1VCC_HARD1
+        - INT_L_X8Y69/VCC_WIRE
+    - wires:
+        - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
+        - $CONSTANTS_X0Y0/$VCC_NODE
+        - SLICE_X11Y69.SLICEL/$VCC_SITE_WIRE
+        - SLICE_X11Y69.SLICEL/CEUSEDVCC_HARD1
+    - wires:
+        - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+        - $CONSTANTS_X0Y0/$GND_NODE
+        - SLICE_X11Y69.SLICEL/$GND_SITE_WIRE
+        - SLICE_X11Y69.SLICEL/SRUSEDGND_HARD0
+bel_pin_test:
+    - bel: SLICE_X14Y63.SLICEL/D6LUT
+      pin: A3
+      wire: SLICE_X14Y63.SLICEL/D3
+    - bel: $CONSTANTS_X0Y0.$CONSTANTS/GND
+      pin: G
+      wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+    - bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC
+      pin: P
+      wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
-- 
cgit v1.2.3