From 77ffdd7fd4e90e0da43e81b1f5e021b08ee64a9f Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Fri, 12 Mar 2021 13:53:09 +0100 Subject: fpga_interchange: tests: add cmake functions Also move all tests in a tests directory Signed-off-by: Alessandro Comodi --- fpga_interchange/examples/const_wire/Makefile | 8 -- fpga_interchange/examples/const_wire/run.tcl | 14 --- fpga_interchange/examples/const_wire/wire.v | 8 -- fpga_interchange/examples/const_wire/wire.xdc | 9 -- fpga_interchange/examples/counter/Makefile | 8 -- fpga_interchange/examples/counter/counter.v | 15 --- fpga_interchange/examples/counter/counter.xdc | 22 ---- fpga_interchange/examples/counter/run.tcl | 15 --- fpga_interchange/examples/ff/Makefile | 8 -- fpga_interchange/examples/ff/ff.v | 11 -- fpga_interchange/examples/ff/ff.xdc | 9 -- fpga_interchange/examples/ff/run.tcl | 14 --- fpga_interchange/examples/lut/Makefile | 8 -- fpga_interchange/examples/lut/lut.v | 5 - fpga_interchange/examples/lut/lut.xdc | 7 -- fpga_interchange/examples/lut/run.tcl | 14 --- fpga_interchange/examples/tests.cmake | 115 +++++++++++++++++++++ fpga_interchange/examples/tests/CMakeLists.txt | 5 + .../examples/tests/const_wire/CMakeLists.txt | 17 +++ fpga_interchange/examples/tests/const_wire/run.tcl | 14 +++ fpga_interchange/examples/tests/const_wire/wire.v | 8 ++ .../examples/tests/const_wire/wire.xdc | 9 ++ .../examples/tests/counter/CMakeLists.txt | 17 +++ fpga_interchange/examples/tests/counter/counter.v | 15 +++ .../examples/tests/counter/counter.xdc | 22 ++++ fpga_interchange/examples/tests/counter/run.tcl | 15 +++ fpga_interchange/examples/tests/ff/CMakeLists.txt | 17 +++ fpga_interchange/examples/tests/ff/ff.v | 11 ++ fpga_interchange/examples/tests/ff/ff.xdc | 9 ++ fpga_interchange/examples/tests/ff/run.tcl | 14 +++ fpga_interchange/examples/tests/lut/CMakeLists.txt | 17 +++ fpga_interchange/examples/tests/lut/lut.v | 5 + fpga_interchange/examples/tests/lut/lut.xdc | 7 ++ fpga_interchange/examples/tests/lut/run.tcl | 14 +++ .../examples/tests/wire/CMakeLists.txt | 17 +++ fpga_interchange/examples/tests/wire/run.tcl | 14 +++ fpga_interchange/examples/tests/wire/wire.v | 5 + fpga_interchange/examples/tests/wire/wire.xdc | 5 + fpga_interchange/examples/wire/Makefile | 8 -- fpga_interchange/examples/wire/run.tcl | 14 --- fpga_interchange/examples/wire/wire.v | 5 - fpga_interchange/examples/wire/wire.xdc | 5 - 42 files changed, 372 insertions(+), 207 deletions(-) delete mode 100644 fpga_interchange/examples/const_wire/Makefile delete mode 100644 fpga_interchange/examples/const_wire/run.tcl delete mode 100644 fpga_interchange/examples/const_wire/wire.v delete mode 100644 fpga_interchange/examples/const_wire/wire.xdc delete mode 100644 fpga_interchange/examples/counter/Makefile delete mode 100644 fpga_interchange/examples/counter/counter.v delete mode 100644 fpga_interchange/examples/counter/counter.xdc delete mode 100644 fpga_interchange/examples/counter/run.tcl delete mode 100644 fpga_interchange/examples/ff/Makefile delete mode 100644 fpga_interchange/examples/ff/ff.v delete mode 100644 fpga_interchange/examples/ff/ff.xdc delete mode 100644 fpga_interchange/examples/ff/run.tcl delete mode 100644 fpga_interchange/examples/lut/Makefile delete mode 100644 fpga_interchange/examples/lut/lut.v delete mode 100644 fpga_interchange/examples/lut/lut.xdc delete mode 100644 fpga_interchange/examples/lut/run.tcl create mode 100644 fpga_interchange/examples/tests.cmake create mode 100644 fpga_interchange/examples/tests/CMakeLists.txt create mode 100644 fpga_interchange/examples/tests/const_wire/CMakeLists.txt create mode 100644 fpga_interchange/examples/tests/const_wire/run.tcl create mode 100644 fpga_interchange/examples/tests/const_wire/wire.v create mode 100644 fpga_interchange/examples/tests/const_wire/wire.xdc create mode 100644 fpga_interchange/examples/tests/counter/CMakeLists.txt create mode 100644 fpga_interchange/examples/tests/counter/counter.v create mode 100644 fpga_interchange/examples/tests/counter/counter.xdc create mode 100644 fpga_interchange/examples/tests/counter/run.tcl create mode 100644 fpga_interchange/examples/tests/ff/CMakeLists.txt create mode 100644 fpga_interchange/examples/tests/ff/ff.v create mode 100644 fpga_interchange/examples/tests/ff/ff.xdc create mode 100644 fpga_interchange/examples/tests/ff/run.tcl create mode 100644 fpga_interchange/examples/tests/lut/CMakeLists.txt create mode 100644 fpga_interchange/examples/tests/lut/lut.v create mode 100644 fpga_interchange/examples/tests/lut/lut.xdc create mode 100644 fpga_interchange/examples/tests/lut/run.tcl create mode 100644 fpga_interchange/examples/tests/wire/CMakeLists.txt create mode 100644 fpga_interchange/examples/tests/wire/run.tcl create mode 100644 fpga_interchange/examples/tests/wire/wire.v create mode 100644 fpga_interchange/examples/tests/wire/wire.xdc delete mode 100644 fpga_interchange/examples/wire/Makefile delete mode 100644 fpga_interchange/examples/wire/run.tcl delete mode 100644 fpga_interchange/examples/wire/wire.v delete mode 100644 fpga_interchange/examples/wire/wire.xdc (limited to 'fpga_interchange') diff --git a/fpga_interchange/examples/const_wire/Makefile b/fpga_interchange/examples/const_wire/Makefile deleted file mode 100644 index 49194f53..00000000 --- a/fpga_interchange/examples/const_wire/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -DESIGN := wire -DESIGN_TOP := top -PACKAGE := csg324 - -include ../template.mk - -build/wire.json: wire.v | build - yosys -c run.tcl diff --git a/fpga_interchange/examples/const_wire/run.tcl b/fpga_interchange/examples/const_wire/run.tcl deleted file mode 100644 index 9127be20..00000000 --- a/fpga_interchange/examples/const_wire/run.tcl +++ /dev/null @@ -1,14 +0,0 @@ -yosys -import - -read_verilog wire.v - -synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp - -# opt_expr -undriven makes sure all nets are driven, if only by the $undef -# net. -opt_expr -undriven -opt_clean - -setundef -zero -params - -write_json build/wire.json diff --git a/fpga_interchange/examples/const_wire/wire.v b/fpga_interchange/examples/const_wire/wire.v deleted file mode 100644 index 5b1ab692..00000000 --- a/fpga_interchange/examples/const_wire/wire.v +++ /dev/null @@ -1,8 +0,0 @@ -module top(output o, output o2, output o3, output o4); - -assign o = 1'b0; -assign o2 = 1'b1; -assign o3 = 1'b0; -assign o4 = 1'b1; - -endmodule diff --git a/fpga_interchange/examples/const_wire/wire.xdc b/fpga_interchange/examples/const_wire/wire.xdc deleted file mode 100644 index 0d96fc45..00000000 --- a/fpga_interchange/examples/const_wire/wire.xdc +++ /dev/null @@ -1,9 +0,0 @@ -set_property PACKAGE_PIN N15 [get_ports o] -set_property PACKAGE_PIN N16 [get_ports o2] -set_property PACKAGE_PIN P17 [get_ports o3] -set_property PACKAGE_PIN R17 [get_ports o4] - -set_property IOSTANDARD LVCMOS33 [get_ports o] -set_property IOSTANDARD LVCMOS33 [get_ports o2] -set_property IOSTANDARD LVCMOS33 [get_ports o3] -set_property IOSTANDARD LVCMOS33 [get_ports o4] diff --git a/fpga_interchange/examples/counter/Makefile b/fpga_interchange/examples/counter/Makefile deleted file mode 100644 index 27d20cdf..00000000 --- a/fpga_interchange/examples/counter/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -DESIGN := counter -DESIGN_TOP := top -PACKAGE := cpg236 - -include ../template.mk - -build/counter.json: counter.v | build - yosys -c run.tcl diff --git a/fpga_interchange/examples/counter/counter.v b/fpga_interchange/examples/counter/counter.v deleted file mode 100644 index 00f52a20..00000000 --- a/fpga_interchange/examples/counter/counter.v +++ /dev/null @@ -1,15 +0,0 @@ -module top(input clk, input rst, output [7:4] io_led); - -reg [31:0] counter = 32'b0; - -assign io_led = counter >> 22; - -always @(posedge clk) -begin - if(rst) - counter <= 32'b0; - else - counter <= counter + 1; -end - -endmodule diff --git a/fpga_interchange/examples/counter/counter.xdc b/fpga_interchange/examples/counter/counter.xdc deleted file mode 100644 index 7cbe67f6..00000000 --- a/fpga_interchange/examples/counter/counter.xdc +++ /dev/null @@ -1,22 +0,0 @@ -## basys3 breakout board -set_property PACKAGE_PIN W5 [get_ports clk] -set_property PACKAGE_PIN V17 [get_ports rst] -#set_property PACKAGE_PIN U16 [get_ports io_led[0]] -#set_property PACKAGE_PIN E19 [get_ports io_led[1]] -#set_property PACKAGE_PIN U19 [get_ports io_led[2]] -#set_property PACKAGE_PIN V19 [get_ports io_led[3]] -set_property PACKAGE_PIN U16 [get_ports io_led[4]] -set_property PACKAGE_PIN E19 [get_ports io_led[5]] -set_property PACKAGE_PIN U19 [get_ports io_led[6]] -set_property PACKAGE_PIN V19 [get_ports io_led[7]] - -set_property IOSTANDARD LVCMOS33 [get_ports clk] -set_property IOSTANDARD LVCMOS33 [get_ports rst] -set_property IOSTANDARD LVCMOS33 [get_ports io_led[4]] -set_property IOSTANDARD LVCMOS33 [get_ports io_led[5]] -set_property IOSTANDARD LVCMOS33 [get_ports io_led[6]] -set_property IOSTANDARD LVCMOS33 [get_ports io_led[7]] -#set_property IOSTANDARD LVCMOS33 [get_ports io_led[0]] -#set_property IOSTANDARD LVCMOS33 [get_ports io_led[1]] -#set_property IOSTANDARD LVCMOS33 [get_ports io_led[2]] -#set_property IOSTANDARD LVCMOS33 [get_ports io_led[3]] diff --git a/fpga_interchange/examples/counter/run.tcl b/fpga_interchange/examples/counter/run.tcl deleted file mode 100644 index 245aab04..00000000 --- a/fpga_interchange/examples/counter/run.tcl +++ /dev/null @@ -1,15 +0,0 @@ -yosys -import - -read_verilog counter.v - -synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp -techmap -map ../remap.v - -# opt_expr -undriven makes sure all nets are driven, if only by the $undef -# net. -opt_expr -undriven -opt_clean - -setundef -zero -params - -write_json build/counter.json diff --git a/fpga_interchange/examples/ff/Makefile b/fpga_interchange/examples/ff/Makefile deleted file mode 100644 index c6118ff7..00000000 --- a/fpga_interchange/examples/ff/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -DESIGN := ff -DESIGN_TOP := top -PACKAGE := csg324 - -include ../template.mk - -build/ff.json: ff.v | build - yosys -c run.tcl diff --git a/fpga_interchange/examples/ff/ff.v b/fpga_interchange/examples/ff/ff.v deleted file mode 100644 index 1c271042..00000000 --- a/fpga_interchange/examples/ff/ff.v +++ /dev/null @@ -1,11 +0,0 @@ -module top(input clk, input d, input r, output reg q); - -always @(posedge clk) -begin - if(r) - q <= 1'b0; - else - q <= d; -end - -endmodule diff --git a/fpga_interchange/examples/ff/ff.xdc b/fpga_interchange/examples/ff/ff.xdc deleted file mode 100644 index 3c132f1d..00000000 --- a/fpga_interchange/examples/ff/ff.xdc +++ /dev/null @@ -1,9 +0,0 @@ -set_property PACKAGE_PIN P17 [get_ports clk] -set_property PACKAGE_PIN N15 [get_ports d] -set_property PACKAGE_PIN N16 [get_ports r] -set_property PACKAGE_PIN M17 [get_ports q] - -set_property IOSTANDARD LVCMOS33 [get_ports clk] -set_property IOSTANDARD LVCMOS33 [get_ports d] -set_property IOSTANDARD LVCMOS33 [get_ports r] -set_property IOSTANDARD LVCMOS33 [get_ports q] diff --git a/fpga_interchange/examples/ff/run.tcl b/fpga_interchange/examples/ff/run.tcl deleted file mode 100644 index 726d86eb..00000000 --- a/fpga_interchange/examples/ff/run.tcl +++ /dev/null @@ -1,14 +0,0 @@ -yosys -import - -read_verilog ff.v - -synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp - -# opt_expr -undriven makes sure all nets are driven, if only by the $undef -# net. -opt_expr -undriven -opt_clean - -setundef -zero -params - -write_json build/ff.json diff --git a/fpga_interchange/examples/lut/Makefile b/fpga_interchange/examples/lut/Makefile deleted file mode 100644 index 54fc8994..00000000 --- a/fpga_interchange/examples/lut/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -DESIGN := lut -DESIGN_TOP := top -PACKAGE := csg324 - -include ../template.mk - -build/lut.json: lut.v | build - yosys -c run.tcl diff --git a/fpga_interchange/examples/lut/lut.v b/fpga_interchange/examples/lut/lut.v deleted file mode 100644 index ca18e665..00000000 --- a/fpga_interchange/examples/lut/lut.v +++ /dev/null @@ -1,5 +0,0 @@ -module top(input i0, input i1, output o); - -assign o = i0 | i1; - -endmodule diff --git a/fpga_interchange/examples/lut/lut.xdc b/fpga_interchange/examples/lut/lut.xdc deleted file mode 100644 index 4f390f25..00000000 --- a/fpga_interchange/examples/lut/lut.xdc +++ /dev/null @@ -1,7 +0,0 @@ -set_property PACKAGE_PIN N16 [get_ports i0] -set_property PACKAGE_PIN N15 [get_ports i1] -set_property PACKAGE_PIN M17 [get_ports o] - -set_property IOSTANDARD LVCMOS33 [get_ports i0] -set_property IOSTANDARD LVCMOS33 [get_ports i1] -set_property IOSTANDARD LVCMOS33 [get_ports o] diff --git a/fpga_interchange/examples/lut/run.tcl b/fpga_interchange/examples/lut/run.tcl deleted file mode 100644 index 1edd8bb7..00000000 --- a/fpga_interchange/examples/lut/run.tcl +++ /dev/null @@ -1,14 +0,0 @@ -yosys -import - -read_verilog lut.v - -synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp - -# opt_expr -undriven makes sure all nets are driven, if only by the $undef -# net. -opt_expr -undriven -opt_clean - -setundef -zero -params - -write_json build/lut.json diff --git a/fpga_interchange/examples/tests.cmake b/fpga_interchange/examples/tests.cmake new file mode 100644 index 00000000..a550fb8f --- /dev/null +++ b/fpga_interchange/examples/tests.cmake @@ -0,0 +1,115 @@ +function(add_interchange_test) + # ~~~ + # add_interchange_test( + # name + # part + # part + # tcl + # xdc + # top + # sources + # ) + # ~~~ + + set(options) + set(oneValueArgs name part package tcl xdc top) + set(multiValueArgs sources) + + cmake_parse_arguments( + add_interchange_test + "${options}" + "${oneValueArgs}" + "${multiValueArgs}" + ${ARGN} + ) + + set(name ${add_interchange_test_name}) + set(part ${add_interchange_test_part}) + set(package ${add_interchange_test_package}) + set(top ${add_interchange_test_top}) + set(tcl ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_tcl}) + set(xdc ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_xdc}) + + set(sources) + foreach(source ${add_interchange_test_sources}) + list(APPEND sources ${CMAKE_CURRENT_SOURCE_DIR}/${source}) + endforeach() + + if (NOT DEFINED top) + # Setting default top value + set(top "top") + endif() + + # Synthesis + set(synth_json ${CMAKE_CURRENT_BINARY_DIR}/${name}.json) + add_custom_command( + OUTPUT ${synth_json} + COMMAND + SOURCES=${sources} + OUT_JSON=${synth_json} + yosys -c ${tcl} + DEPENDS ${sources} + ) + + add_custom_target(test-${family}-${name}-json DEPENDS ${synth_json}) + + # Logical Netlist + set(device_target constraints-luts-${part}-device) + get_property(device_loc TARGET constraints-luts-${part}-device PROPERTY LOCATION) + + set(netlist ${CMAKE_CURRENT_BINARY_DIR}/${name}.netlist) + add_custom_command( + OUTPUT ${netlist} + COMMAND + python3 -mfpga_interchange.yosys_json + --schema_dir ${INTERCHANGE_SCHEMA_PATH} + --device ${device_loc} + --top ${top} + ${synth_json} + ${netlist} + DEPENDS + ${synth_json} + ${device_target} + ) + + add_custom_target(test-${family}-${name}-netlist DEPENDS ${netlist}) + + set(chipdb_target chipdb-${part}-bba) + + # Physical Netlist + set(phys ${CMAKE_CURRENT_BINARY_DIR}/${name}.phys) + add_custom_command( + OUTPUT ${phys} + COMMAND + nextpnr-fpga_interchange + --chipdb ${chipdb_dir}/chipdb-${part}.bba + --xdc ${xdc} + --netlist ${netlist} + --phys ${phys} + --package ${package} + DEPENDS + ${netlist} + ${chipdb_target} + ) + + add_custom_target(test-${family}-${name}-phys DEPENDS ${phys}) + + set(dcp ${CMAKE_CURRENT_BINARY_DIR}/${name}.dcp) + add_custom_command( + OUTPUT ${dcp} + COMMAND + RAPIDWRIGHT_PATH=${RAPIDWRIGHT_PATH} + ${RAPIDWRIGHT_PATH}/scripts/invoke_rapidwright.sh + com.xilinx.rapidwright.interchange.PhysicalNetlistToDcp + ${netlist} ${phys} ${xdc} ${dcp} + DEPENDS + ${phys} + ${netlist} + ) + + add_custom_target(test-${family}-${name}-dcp DEPENDS ${dcp}) + add_dependencies(all-${family}-tests test-${family}-${name}-dcp) +endfunction() + +add_custom_target(all-${family}-tests) +add_subdirectory(${family}/examples/tests) diff --git a/fpga_interchange/examples/tests/CMakeLists.txt b/fpga_interchange/examples/tests/CMakeLists.txt new file mode 100644 index 00000000..49b5b587 --- /dev/null +++ b/fpga_interchange/examples/tests/CMakeLists.txt @@ -0,0 +1,5 @@ +add_subdirectory(wire) +add_subdirectory(const_wire) +add_subdirectory(counter) +add_subdirectory(ff) +add_subdirectory(lut) diff --git a/fpga_interchange/examples/tests/const_wire/CMakeLists.txt b/fpga_interchange/examples/tests/const_wire/CMakeLists.txt new file mode 100644 index 00000000..163f4a97 --- /dev/null +++ b/fpga_interchange/examples/tests/const_wire/CMakeLists.txt @@ -0,0 +1,17 @@ +add_interchange_test( + name const_wire_basys3 + part xc7a35tcpg236-1 + package cpg236 + tcl run.tcl + xdc wire.xdc + sources wire.v +) + +add_interchange_test( + name const_wire_arty + part xc7a35tcsg324-1 + package csg324 + tcl run.tcl + xdc wire.xdc + sources wire.v +) diff --git a/fpga_interchange/examples/tests/const_wire/run.tcl b/fpga_interchange/examples/tests/const_wire/run.tcl new file mode 100644 index 00000000..b8d0df72 --- /dev/null +++ b/fpga_interchange/examples/tests/const_wire/run.tcl @@ -0,0 +1,14 @@ +yosys -import + +read_verilog $::env(SOURCES) + +synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json $::env(OUT_JSON) diff --git a/fpga_interchange/examples/tests/const_wire/wire.v b/fpga_interchange/examples/tests/const_wire/wire.v new file mode 100644 index 00000000..5b1ab692 --- /dev/null +++ b/fpga_interchange/examples/tests/const_wire/wire.v @@ -0,0 +1,8 @@ +module top(output o, output o2, output o3, output o4); + +assign o = 1'b0; +assign o2 = 1'b1; +assign o3 = 1'b0; +assign o4 = 1'b1; + +endmodule diff --git a/fpga_interchange/examples/tests/const_wire/wire.xdc b/fpga_interchange/examples/tests/const_wire/wire.xdc new file mode 100644 index 00000000..0d96fc45 --- /dev/null +++ b/fpga_interchange/examples/tests/const_wire/wire.xdc @@ -0,0 +1,9 @@ +set_property PACKAGE_PIN N15 [get_ports o] +set_property PACKAGE_PIN N16 [get_ports o2] +set_property PACKAGE_PIN P17 [get_ports o3] +set_property PACKAGE_PIN R17 [get_ports o4] + +set_property IOSTANDARD LVCMOS33 [get_ports o] +set_property IOSTANDARD LVCMOS33 [get_ports o2] +set_property IOSTANDARD LVCMOS33 [get_ports o3] +set_property IOSTANDARD LVCMOS33 [get_ports o4] diff --git a/fpga_interchange/examples/tests/counter/CMakeLists.txt b/fpga_interchange/examples/tests/counter/CMakeLists.txt new file mode 100644 index 00000000..e105a86a --- /dev/null +++ b/fpga_interchange/examples/tests/counter/CMakeLists.txt @@ -0,0 +1,17 @@ +add_interchange_test( + name counter_basys3 + part xc7a35tcpg236-1 + package cpg236 + tcl run.tcl + xdc counter.xdc + sources counter.v +) + +add_interchange_test( + name counter_arty + part xc7a35tcsg324-1 + package csg324 + tcl run.tcl + xdc counter.xdc + sources counter.v +) diff --git a/fpga_interchange/examples/tests/counter/counter.v b/fpga_interchange/examples/tests/counter/counter.v new file mode 100644 index 00000000..00f52a20 --- /dev/null +++ b/fpga_interchange/examples/tests/counter/counter.v @@ -0,0 +1,15 @@ +module top(input clk, input rst, output [7:4] io_led); + +reg [31:0] counter = 32'b0; + +assign io_led = counter >> 22; + +always @(posedge clk) +begin + if(rst) + counter <= 32'b0; + else + counter <= counter + 1; +end + +endmodule diff --git a/fpga_interchange/examples/tests/counter/counter.xdc b/fpga_interchange/examples/tests/counter/counter.xdc new file mode 100644 index 00000000..7cbe67f6 --- /dev/null +++ b/fpga_interchange/examples/tests/counter/counter.xdc @@ -0,0 +1,22 @@ +## basys3 breakout board +set_property PACKAGE_PIN W5 [get_ports clk] +set_property PACKAGE_PIN V17 [get_ports rst] +#set_property PACKAGE_PIN U16 [get_ports io_led[0]] +#set_property PACKAGE_PIN E19 [get_ports io_led[1]] +#set_property PACKAGE_PIN U19 [get_ports io_led[2]] +#set_property PACKAGE_PIN V19 [get_ports io_led[3]] +set_property PACKAGE_PIN U16 [get_ports io_led[4]] +set_property PACKAGE_PIN E19 [get_ports io_led[5]] +set_property PACKAGE_PIN U19 [get_ports io_led[6]] +set_property PACKAGE_PIN V19 [get_ports io_led[7]] + +set_property IOSTANDARD LVCMOS33 [get_ports clk] +set_property IOSTANDARD LVCMOS33 [get_ports rst] +set_property IOSTANDARD LVCMOS33 [get_ports io_led[4]] +set_property IOSTANDARD LVCMOS33 [get_ports io_led[5]] +set_property IOSTANDARD LVCMOS33 [get_ports io_led[6]] +set_property IOSTANDARD LVCMOS33 [get_ports io_led[7]] +#set_property IOSTANDARD LVCMOS33 [get_ports io_led[0]] +#set_property IOSTANDARD LVCMOS33 [get_ports io_led[1]] +#set_property IOSTANDARD LVCMOS33 [get_ports io_led[2]] +#set_property IOSTANDARD LVCMOS33 [get_ports io_led[3]] diff --git a/fpga_interchange/examples/tests/counter/run.tcl b/fpga_interchange/examples/tests/counter/run.tcl new file mode 100644 index 00000000..7cd9f10f --- /dev/null +++ b/fpga_interchange/examples/tests/counter/run.tcl @@ -0,0 +1,15 @@ +yosys -import + +read_verilog $::env(SOURCES) + +synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp +techmap -map ../remap.v + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json $::env(OUT_JSON) diff --git a/fpga_interchange/examples/tests/ff/CMakeLists.txt b/fpga_interchange/examples/tests/ff/CMakeLists.txt new file mode 100644 index 00000000..66074c64 --- /dev/null +++ b/fpga_interchange/examples/tests/ff/CMakeLists.txt @@ -0,0 +1,17 @@ +add_interchange_test( + name ff_basys3 + part xc7a35tcpg236-1 + package cpg236 + tcl run.tcl + xdc ff.xdc + sources ff.v +) + +add_interchange_test( + name ff_arty + part xc7a35tcsg324-1 + package csg324 + tcl run.tcl + xdc ff.xdc + sources ff.v +) diff --git a/fpga_interchange/examples/tests/ff/ff.v b/fpga_interchange/examples/tests/ff/ff.v new file mode 100644 index 00000000..1c271042 --- /dev/null +++ b/fpga_interchange/examples/tests/ff/ff.v @@ -0,0 +1,11 @@ +module top(input clk, input d, input r, output reg q); + +always @(posedge clk) +begin + if(r) + q <= 1'b0; + else + q <= d; +end + +endmodule diff --git a/fpga_interchange/examples/tests/ff/ff.xdc b/fpga_interchange/examples/tests/ff/ff.xdc new file mode 100644 index 00000000..3c132f1d --- /dev/null +++ b/fpga_interchange/examples/tests/ff/ff.xdc @@ -0,0 +1,9 @@ +set_property PACKAGE_PIN P17 [get_ports clk] +set_property PACKAGE_PIN N15 [get_ports d] +set_property PACKAGE_PIN N16 [get_ports r] +set_property PACKAGE_PIN M17 [get_ports q] + +set_property IOSTANDARD LVCMOS33 [get_ports clk] +set_property IOSTANDARD LVCMOS33 [get_ports d] +set_property IOSTANDARD LVCMOS33 [get_ports r] +set_property IOSTANDARD LVCMOS33 [get_ports q] diff --git a/fpga_interchange/examples/tests/ff/run.tcl b/fpga_interchange/examples/tests/ff/run.tcl new file mode 100644 index 00000000..b8d0df72 --- /dev/null +++ b/fpga_interchange/examples/tests/ff/run.tcl @@ -0,0 +1,14 @@ +yosys -import + +read_verilog $::env(SOURCES) + +synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json $::env(OUT_JSON) diff --git a/fpga_interchange/examples/tests/lut/CMakeLists.txt b/fpga_interchange/examples/tests/lut/CMakeLists.txt new file mode 100644 index 00000000..4ec74b3d --- /dev/null +++ b/fpga_interchange/examples/tests/lut/CMakeLists.txt @@ -0,0 +1,17 @@ +add_interchange_test( + name lut_basys3 + part xc7a35tcpg236-1 + package cpg236 + tcl run.tcl + xdc lut.xdc + sources lut.v +) + +add_interchange_test( + name lut_arty + part xc7a35tcsg324-1 + package csg324 + tcl run.tcl + xdc lut.xdc + sources lut.v +) diff --git a/fpga_interchange/examples/tests/lut/lut.v b/fpga_interchange/examples/tests/lut/lut.v new file mode 100644 index 00000000..ca18e665 --- /dev/null +++ b/fpga_interchange/examples/tests/lut/lut.v @@ -0,0 +1,5 @@ +module top(input i0, input i1, output o); + +assign o = i0 | i1; + +endmodule diff --git a/fpga_interchange/examples/tests/lut/lut.xdc b/fpga_interchange/examples/tests/lut/lut.xdc new file mode 100644 index 00000000..4f390f25 --- /dev/null +++ b/fpga_interchange/examples/tests/lut/lut.xdc @@ -0,0 +1,7 @@ +set_property PACKAGE_PIN N16 [get_ports i0] +set_property PACKAGE_PIN N15 [get_ports i1] +set_property PACKAGE_PIN M17 [get_ports o] + +set_property IOSTANDARD LVCMOS33 [get_ports i0] +set_property IOSTANDARD LVCMOS33 [get_ports i1] +set_property IOSTANDARD LVCMOS33 [get_ports o] diff --git a/fpga_interchange/examples/tests/lut/run.tcl b/fpga_interchange/examples/tests/lut/run.tcl new file mode 100644 index 00000000..b8d0df72 --- /dev/null +++ b/fpga_interchange/examples/tests/lut/run.tcl @@ -0,0 +1,14 @@ +yosys -import + +read_verilog $::env(SOURCES) + +synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json $::env(OUT_JSON) diff --git a/fpga_interchange/examples/tests/wire/CMakeLists.txt b/fpga_interchange/examples/tests/wire/CMakeLists.txt new file mode 100644 index 00000000..7736877f --- /dev/null +++ b/fpga_interchange/examples/tests/wire/CMakeLists.txt @@ -0,0 +1,17 @@ +add_interchange_test( + name wire_basys3 + part xc7a35tcpg236-1 + package cpg236 + tcl run.tcl + xdc wire.xdc + sources wire.v +) + +add_interchange_test( + name wire_arty + part xc7a35tcsg324-1 + package csg324 + tcl run.tcl + xdc wire.xdc + sources wire.v +) diff --git a/fpga_interchange/examples/tests/wire/run.tcl b/fpga_interchange/examples/tests/wire/run.tcl new file mode 100644 index 00000000..b8d0df72 --- /dev/null +++ b/fpga_interchange/examples/tests/wire/run.tcl @@ -0,0 +1,14 @@ +yosys -import + +read_verilog $::env(SOURCES) + +synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json $::env(OUT_JSON) diff --git a/fpga_interchange/examples/tests/wire/wire.v b/fpga_interchange/examples/tests/wire/wire.v new file mode 100644 index 00000000..429d05ff --- /dev/null +++ b/fpga_interchange/examples/tests/wire/wire.v @@ -0,0 +1,5 @@ +module top(input i, output o); + +assign o = i; + +endmodule diff --git a/fpga_interchange/examples/tests/wire/wire.xdc b/fpga_interchange/examples/tests/wire/wire.xdc new file mode 100644 index 00000000..c923f0fc --- /dev/null +++ b/fpga_interchange/examples/tests/wire/wire.xdc @@ -0,0 +1,5 @@ +set_property PACKAGE_PIN N16 [get_ports i] +set_property PACKAGE_PIN N15 [get_ports o] + +set_property IOSTANDARD LVCMOS33 [get_ports i] +set_property IOSTANDARD LVCMOS33 [get_ports o] diff --git a/fpga_interchange/examples/wire/Makefile b/fpga_interchange/examples/wire/Makefile deleted file mode 100644 index 49194f53..00000000 --- a/fpga_interchange/examples/wire/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -DESIGN := wire -DESIGN_TOP := top -PACKAGE := csg324 - -include ../template.mk - -build/wire.json: wire.v | build - yosys -c run.tcl diff --git a/fpga_interchange/examples/wire/run.tcl b/fpga_interchange/examples/wire/run.tcl deleted file mode 100644 index 9127be20..00000000 --- a/fpga_interchange/examples/wire/run.tcl +++ /dev/null @@ -1,14 +0,0 @@ -yosys -import - -read_verilog wire.v - -synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp - -# opt_expr -undriven makes sure all nets are driven, if only by the $undef -# net. -opt_expr -undriven -opt_clean - -setundef -zero -params - -write_json build/wire.json diff --git a/fpga_interchange/examples/wire/wire.v b/fpga_interchange/examples/wire/wire.v deleted file mode 100644 index 429d05ff..00000000 --- a/fpga_interchange/examples/wire/wire.v +++ /dev/null @@ -1,5 +0,0 @@ -module top(input i, output o); - -assign o = i; - -endmodule diff --git a/fpga_interchange/examples/wire/wire.xdc b/fpga_interchange/examples/wire/wire.xdc deleted file mode 100644 index c923f0fc..00000000 --- a/fpga_interchange/examples/wire/wire.xdc +++ /dev/null @@ -1,5 +0,0 @@ -set_property PACKAGE_PIN N16 [get_ports i] -set_property PACKAGE_PIN N15 [get_ports o] - -set_property IOSTANDARD LVCMOS33 [get_ports i] -set_property IOSTANDARD LVCMOS33 [get_ports o] -- cgit v1.2.3