From 4e346ecfba86880c2528e3463b9beb42932d8567 Mon Sep 17 00:00:00 2001 From: gatecat Date: Wed, 14 Apr 2021 10:14:51 +0100 Subject: Hash table refactoring Signed-off-by: gatecat --- fpga_interchange/cell_parameters.h | 2 +- fpga_interchange/cost_map.cc | 2 +- fpga_interchange/cost_map.h | 2 +- fpga_interchange/lookahead.cc | 5 +++-- fpga_interchange/pseudo_pip_model.h | 2 +- fpga_interchange/site_router.cc | 8 ++++---- 6 files changed, 11 insertions(+), 10 deletions(-) (limited to 'fpga_interchange') diff --git a/fpga_interchange/cell_parameters.h b/fpga_interchange/cell_parameters.h index 3507a81f..de82e76b 100644 --- a/fpga_interchange/cell_parameters.h +++ b/fpga_interchange/cell_parameters.h @@ -42,7 +42,7 @@ struct CellParameters bool compare_property(const Context *ctx, IdString cell_type, IdString parameter, const Property &property, IdString value_to_compare) const; - HashTables::HashMap, const CellParameterPOD *> parameters; + HashTables::HashMap, const CellParameterPOD *, PairHash> parameters; std::regex verilog_binary_re; std::regex verilog_hex_re; diff --git a/fpga_interchange/cost_map.cc b/fpga_interchange/cost_map.cc index b42f115d..868fdca0 100644 --- a/fpga_interchange/cost_map.cc +++ b/fpga_interchange/cost_map.cc @@ -121,7 +121,7 @@ delay_t CostMap::get_delay(const Context *ctx, WireId src_wire, WireId dst_wire) } void CostMap::set_cost_map(const Context *ctx, const TypeWirePair &wire_pair, - const HashTables::HashMap, delay_t> &delays) + const HashTables::HashMap, delay_t, PairHash> &delays) { CostMapEntry delay_matrix; diff --git a/fpga_interchange/cost_map.h b/fpga_interchange/cost_map.h index e57a1027..810d0198 100644 --- a/fpga_interchange/cost_map.h +++ b/fpga_interchange/cost_map.h @@ -39,7 +39,7 @@ class CostMap public: delay_t get_delay(const Context *ctx, WireId src, WireId dst) const; void set_cost_map(const Context *ctx, const TypeWirePair &wire_pair, - const HashTables::HashMap, delay_t> &delays); + const HashTables::HashMap, delay_t, PairHash> &delays); void from_reader(lookahead_storage::CostMap::Reader reader); void to_builder(lookahead_storage::CostMap::Builder builder) const; diff --git a/fpga_interchange/lookahead.cc b/fpga_interchange/lookahead.cc index cd05c16f..6dc8c43a 100644 --- a/fpga_interchange/lookahead.cc +++ b/fpga_interchange/lookahead.cc @@ -250,7 +250,7 @@ static void expand_input_type(const Context *ctx, DeterministicRNG *rng, const S struct DelayStorage { - HashTables::HashMap, delay_t>> storage; + HashTables::HashMap, delay_t, PairHash>> storage; int32_t max_explore_depth; }; @@ -996,7 +996,8 @@ void Lookahead::build_lookahead(const Context *ctx, DeterministicRNG *rng) #if defined(NEXTPNR_USE_TBB) // Run parallely tbb::parallel_for_each( all_tiles_storage.storage, - [&](const std::pair, delay_t>> &type_pair) { + [&](const std::pair, delay_t, PairHash>> + &type_pair) { #else for (const auto &type_pair : all_tiles_storage.storage) { #endif diff --git a/fpga_interchange/pseudo_pip_model.h b/fpga_interchange/pseudo_pip_model.h index 53e2b3a3..1e79071d 100644 --- a/fpga_interchange/pseudo_pip_model.h +++ b/fpga_interchange/pseudo_pip_model.h @@ -98,7 +98,7 @@ struct PseudoPipData const std::vector &get_logic_bels_for_pip(const Context *ctx, int32_t site, PipId pip) const; HashTables::HashMap max_pseudo_pip_for_tile_type; - HashTables::HashMap, std::vector> possibles_sites_for_pip; + HashTables::HashMap, std::vector, PairHash> possibles_sites_for_pip; HashTables::HashMap> logic_bels_for_pip; }; diff --git a/fpga_interchange/site_router.cc b/fpga_interchange/site_router.cc index 51b8bef3..f8cc2208 100644 --- a/fpga_interchange/site_router.cc +++ b/fpga_interchange/site_router.cc @@ -988,7 +988,7 @@ static void apply_routing(Context *ctx, const SiteArch &site_arch) } static bool map_luts_in_site(const SiteInformation &site_info, - HashTables::HashSet> *blocked_wires) + HashTables::HashSet, PairHash> *blocked_wires) { const Context *ctx = site_info.ctx; const std::vector &lut_elements = ctx->lut_elements.at(site_info.tile_type); @@ -1031,7 +1031,7 @@ static bool map_luts_in_site(const SiteInformation &site_info, // Block outputs of unavailable LUTs to prevent site router from using them. static void block_lut_outputs(SiteArch *site_arch, - const HashTables::HashSet> &blocked_wires) + const HashTables::HashSet, PairHash> &blocked_wires) { const Context *ctx = site_arch->site_info->ctx; auto &tile_info = ctx->chip_info->tile_types[site_arch->site_info->tile_type]; @@ -1112,7 +1112,7 @@ bool SiteRouter::checkSiteRouting(const Context *ctx, const TileStatus &tile_sta } SiteInformation site_info(ctx, tile, site, cells_in_site); - HashTables::HashSet> blocked_wires; + HashTables::HashSet, PairHash> blocked_wires; if (!map_luts_in_site(site_info, &blocked_wires)) { site_ok = false; return site_ok; @@ -1190,7 +1190,7 @@ void SiteRouter::bindSiteRouting(Context *ctx) } SiteInformation site_info(ctx, tile, site, cells_in_site); - HashTables::HashSet> blocked_wires; + HashTables::HashSet, PairHash> blocked_wires; NPNR_ASSERT(map_luts_in_site(site_info, &blocked_wires)); SiteArch site_arch(&site_info); -- cgit v1.2.3