From 4cd74bba2c010e4d714ec72fe11128069ea0495a Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Fri, 19 Mar 2021 17:18:01 -0700
Subject: Add getBelPinType to Python interface.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 fpga_interchange/examples/devices/xc7a35t/test_data.yaml | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'fpga_interchange')

diff --git a/fpga_interchange/examples/devices/xc7a35t/test_data.yaml b/fpga_interchange/examples/devices/xc7a35t/test_data.yaml
index 268d180a..88c6feda 100644
--- a/fpga_interchange/examples/devices/xc7a35t/test_data.yaml
+++ b/fpga_interchange/examples/devices/xc7a35t/test_data.yaml
@@ -34,3 +34,7 @@ bel_pin_test:
     - bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC
       pin: P
       wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
+    - bel: SLICE_X1Y19.SLICEL/SRUSEDGND
+      pin: "0"
+      wire: SLICE_X1Y19.SLICEL/SRUSEDGND_HARD0
+      type: PORT_OUT
-- 
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