From 32327b761ab8b8c438bd91d6c32f061ffaed3454 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Mon, 1 Apr 2019 20:16:29 +0100
Subject: generic: Simple working example

Signed-off-by: David Shah <dave@ds0.me>
---
 generic/examples/.gitignore |  1 +
 generic/examples/README.md  | 11 +++++++++++
 generic/examples/blinky.v   |  9 +++++++++
 generic/examples/report.py  | 13 +++++++++++++
 generic/examples/simple.sh  |  4 ++++
 generic/examples/simple.v   | 15 ---------------
 6 files changed, 38 insertions(+), 15 deletions(-)
 create mode 100644 generic/examples/.gitignore
 create mode 100644 generic/examples/README.md
 create mode 100644 generic/examples/blinky.v
 create mode 100644 generic/examples/report.py
 create mode 100755 generic/examples/simple.sh
 delete mode 100644 generic/examples/simple.v

(limited to 'generic/examples')

diff --git a/generic/examples/.gitignore b/generic/examples/.gitignore
new file mode 100644
index 00000000..83d79a7d
--- /dev/null
+++ b/generic/examples/.gitignore
@@ -0,0 +1 @@
+blinky.txt
diff --git a/generic/examples/README.md b/generic/examples/README.md
new file mode 100644
index 00000000..5eb0ea72
--- /dev/null
+++ b/generic/examples/README.md
@@ -0,0 +1,11 @@
+# Generic Architecture Example
+
+This contains a simple, artificial, example of the nextpnr generic API.
+
+ - simple.py procedurally generates a simple FPGA architecture with IO at the edges,
+   logic slices in all other tiles, and interconnect only between adjacent tiles
+
+ - report.py stores design information after place-and-route to blinky.txt in place
+   of real bitstream generation
+
+ - Run blinky.sh to build an example design on the FPGA above
\ No newline at end of file
diff --git a/generic/examples/blinky.v b/generic/examples/blinky.v
new file mode 100644
index 00000000..b7cb1b86
--- /dev/null
+++ b/generic/examples/blinky.v
@@ -0,0 +1,9 @@
+module top(input clk, output reg [7:0] leds);
+
+reg [25:0] ctr;
+always @(posedge clk)
+	ctr <= ctr + 1'b1;
+
+assign leds = ctr[25:18];
+
+endmodule
\ No newline at end of file
diff --git a/generic/examples/report.py b/generic/examples/report.py
new file mode 100644
index 00000000..c43367fa
--- /dev/null
+++ b/generic/examples/report.py
@@ -0,0 +1,13 @@
+with open("blinky.txt", "w") as f:
+	for nname, net in ctx.nets:
+		print("# Net %s" % nname, file=f)
+		# FIXME: Pip ordering
+		for wire, pip in net.wires:
+			if pip.pip != "":
+				print("%s" % pip.pip, file=f)
+		print("", file=f)
+	for cname, cell in ctx.cells:
+		print("# Cell %s at %s" % (cname, cell.bel), file=f)
+		for param, val in cell.params:
+			print("%s.%s %s" % (cell.bel, param, val), file=f)
+		print("", file=f)
\ No newline at end of file
diff --git a/generic/examples/simple.sh b/generic/examples/simple.sh
new file mode 100755
index 00000000..ed800639
--- /dev/null
+++ b/generic/examples/simple.sh
@@ -0,0 +1,4 @@
+#!/usr/bin/bash
+set -ex
+yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v
+../../nextpnr-generic --pre-pack simple.py --json blinky.json --post-route report.py
\ No newline at end of file
diff --git a/generic/examples/simple.v b/generic/examples/simple.v
deleted file mode 100644
index 6d337101..00000000
--- a/generic/examples/simple.v
+++ /dev/null
@@ -1,15 +0,0 @@
-(* blackbox *)
-module SLICE_LUT4(
-	input I0, I1, I2, I3,
-	input CLK,
-	output Q
-);
-parameter INIT = 16'h0000;
-parameter FF_USED = 1'b0;
-endmodule
-
-module top(input a, output q);
-
-SLICE_LUT4 sl_i(.I0(a), .Q(q));
-
-endmodule
\ No newline at end of file
-- 
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