From cabdfe361655a9eb8132ff5c7afe8c1fa7a3847b Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 15 Jun 2018 21:29:02 +0200 Subject: ice40: Only place IO at valid pins Signed-off-by: David Shah --- ice40/arch_place.cc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'ice40/arch_place.cc') diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc index e4a6c5d7..492ed846 100644 --- a/ice40/arch_place.cc +++ b/ice40/arch_place.cc @@ -22,8 +22,8 @@ NEXTPNR_NAMESPACE_BEGIN -static const NetInfo * -get_net_or_nullptr(const CellInfo *cell, const IdString port) +static const NetInfo *get_net_or_nullptr(const CellInfo *cell, + const IdString port) { auto found = cell->ports.find(port); if (found != cell->ports.end()) @@ -97,7 +97,8 @@ bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel) cells.push_back(cell); return logicCellsCompatible(cells); - + } else if (cell->type == "SB_IO") { + return design->chip.getBelPackagePin(bel) != ""; } else { // TODO: IO cell clock checks return true; -- cgit v1.2.3