From 5a9ff4aea15fca7bcf8c86eaa1f92eb51f551e5b Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 12 Jun 2018 14:39:49 +0200 Subject: ice40: Testing the placement validity check Signed-off-by: David Shah --- ice40/pack_tests/locals.v | 27 +++++++++++++++++++++++++++ ice40/pack_tests/test.sh | 2 +- 2 files changed, 28 insertions(+), 1 deletion(-) create mode 100644 ice40/pack_tests/locals.v (limited to 'ice40/pack_tests') diff --git a/ice40/pack_tests/locals.v b/ice40/pack_tests/locals.v new file mode 100644 index 00000000..a1c5ea9f --- /dev/null +++ b/ice40/pack_tests/locals.v @@ -0,0 +1,27 @@ +module top(input clk, cen, rst, ina, inb, output outa, outb, outc, outd); + +reg [31:0] temp = 0; + +integer i; + +always @(posedge clk) +begin + if (cen) begin + if (rst) begin + temp <= 0; + end else begin + temp[0] <= ina; + temp[1] <= inb; + for (i = 2; i < 32; i++) begin + temp[i] <= temp[(i + 3) % 32] ^ temp[(i + 30) % 32] ^ temp[(i + 4) % 16] ^ temp[(i + 2) % 32]; + end + end + end +end + +assign outa = temp[3]; +assign outb = temp[5]; +assign outc = temp[9]; +assign outd = temp[15]; + +endmodule diff --git a/ice40/pack_tests/test.sh b/ice40/pack_tests/test.sh index 7ac3ef76..88ff5b1d 100755 --- a/ice40/pack_tests/test.sh +++ b/ice40/pack_tests/test.sh @@ -12,4 +12,4 @@ yosys -p "rename chip gate;\ proc;\ clk2fflogic;\ miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter;\ - sat -dump_vcd equiv_${NAME}.vcd -verify-no-timeout -timeout 20 -seq 10 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter" ${NAME}_out.v + sat -dump_vcd equiv_${NAME}.vcd -verify-no-timeout -timeout 60 -seq 50 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter" ${NAME}_out.v -- cgit v1.2.3