From c4cb0c5e4951f832f1d416013add1177face3900 Mon Sep 17 00:00:00 2001 From: Sylvain Munaut Date: Wed, 17 Apr 2019 16:05:48 +0200 Subject: ice40: In assignCellInfo get PIN_TYPE/NEG_TRIGGER from params and not attrs Signed-off-by: Sylvain Munaut --- ice40/arch.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'ice40') diff --git a/ice40/arch.cc b/ice40/arch.cc index bfcadc0b..d536ad35 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -1221,8 +1221,8 @@ void Arch::assignCellInfo(CellInfo *cell) } else if (cell->type == id_SB_IO) { cell->ioInfo.lvds = str_or_default(cell->params, id_IO_STANDARD, "SB_LVCMOS") == "SB_LVDS_INPUT"; cell->ioInfo.global = bool_or_default(cell->attrs, this->id("GLOBAL")); - cell->ioInfo.pintype = int_or_default(cell->attrs, this->id("PIN_TYPE")); - cell->ioInfo.negtrig = bool_or_default(cell->attrs, this->id("NEG_TRIGGER")); + cell->ioInfo.pintype = int_or_default(cell->params, this->id("PIN_TYPE")); + cell->ioInfo.negtrig = bool_or_default(cell->params, this->id("NEG_TRIGGER")); } else if (cell->type == id_SB_GB) { cell->gbInfo.forPadIn = bool_or_default(cell->attrs, this->id("FOR_PAD_IN")); -- cgit v1.2.3 From 66b64f928b97c94292751d94832c13fc47f2f122 Mon Sep 17 00:00:00 2001 From: Sylvain Munaut Date: Wed, 17 Apr 2019 14:07:38 +0200 Subject: ice40: Check for SB_IO shared wires conflicts in isValidBelForCell Signed-off-by: Sylvain Munaut --- ice40/arch_place.cc | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'ice40') diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc index 90bb62b9..ede8d47f 100644 --- a/ice40/arch_place.cc +++ b/ice40/arch_place.cc @@ -91,6 +91,18 @@ bool Arch::isBelLocationValid(BelId bel) const } } +static inline bool _io_pintype_need_clk_in(unsigned pin_type) { return (pin_type & 0x01) == 0x00; } + +static inline bool _io_pintype_need_clk_out(unsigned pin_type) +{ + return ((pin_type & 0x30) == 0x30) || ((pin_type & 0x3c) && ((pin_type & 0x0c) != 0x08)); +} + +static inline bool _io_pintype_need_clk_en(unsigned pin_type) +{ + return _io_pintype_need_clk_in(pin_type) || _io_pintype_need_clk_out(pin_type); +} + bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const { if (cell->type == id_ICESTORM_LC) { @@ -157,6 +169,30 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const CellInfo *compCell = getBoundBelCell(compBel); if (compCell && compCell->ioInfo.lvds) return false; + + // Check for conflicts on shared nets + // - CLOCK_ENABLE + // - OUTPUT_CLK + // - INPUT_CLK + if (compCell) { + bool use[6] = { + _io_pintype_need_clk_in(cell->ioInfo.pintype), + _io_pintype_need_clk_in(compCell->ioInfo.pintype), + _io_pintype_need_clk_out(cell->ioInfo.pintype), + _io_pintype_need_clk_out(compCell->ioInfo.pintype), + _io_pintype_need_clk_en(cell->ioInfo.pintype), + _io_pintype_need_clk_en(compCell->ioInfo.pintype), + }; + NetInfo *nets[] = { + cell->ports[id_INPUT_CLK].net, compCell->ports[id_INPUT_CLK].net, + cell->ports[id_OUTPUT_CLK].net, compCell->ports[id_OUTPUT_CLK].net, + cell->ports[id_CLOCK_ENABLE].net, compCell->ports[id_CLOCK_ENABLE].net, + }; + + for (int i = 0; i < 6; i++) + if (use[i] && (nets[i] != nets[i ^ 1]) && (use[i ^ 1] || (nets[i ^ 1] != nullptr))) + return false; + } } return getBelPackagePin(bel) != ""; -- cgit v1.2.3