From 391d49c13ec675e263115d18481d4b842622b712 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 12 Jun 2018 14:24:59 +0200 Subject: Add nextpnr namespace Signed-off-by: Clifford Wolf --- ice40/bitstream.cc | 4 ++++ ice40/bitstream.h | 4 ++++ ice40/cells.cc | 4 ++++ ice40/cells.h | 4 ++++ ice40/chip.cc | 4 ++++ ice40/chip.h | 20 ++++++++++++++------ ice40/chipdb.py | 9 ++++++++- ice40/family.cmake | 1 + ice40/pybindings.cc | 4 ++++ 9 files changed, 47 insertions(+), 7 deletions(-) (limited to 'ice40') diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 944e80c2..7952a8a1 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -20,6 +20,8 @@ #include "bitstream.h" #include +NEXTPNR_NAMESPACE_BEGIN + inline TileType tile_at(const Chip &chip, int x, int y) { return chip.chip_info.tile_grid[y * chip.chip_info.width + x]; @@ -311,3 +313,5 @@ void write_asc(const Design &design, std::ostream &out) } } } + +NEXTPNR_NAMESPACE_END diff --git a/ice40/bitstream.h b/ice40/bitstream.h index fecc14e1..11547163 100644 --- a/ice40/bitstream.h +++ b/ice40/bitstream.h @@ -23,6 +23,10 @@ #include #include "nextpnr.h" +NEXTPNR_NAMESPACE_BEGIN + void write_asc(const Design &design, std::ostream &out); +NEXTPNR_NAMESPACE_END + #endif diff --git a/ice40/cells.cc b/ice40/cells.cc index 328b5f2d..1e9a012b 100644 --- a/ice40/cells.cc +++ b/ice40/cells.cc @@ -21,6 +21,8 @@ #include "design_utils.h" #include "log.h" +NEXTPNR_NAMESPACE_BEGIN + static void add_port(CellInfo *cell, IdString name, PortType dir) { cell->ports[name] = PortInfo{name, nullptr, dir}; @@ -108,3 +110,5 @@ void dff_to_lc(CellInfo *dff, CellInfo *lc, bool pass_thru_lut) replace_port(dff, "D", lc, "I0"); } } + +NEXTPNR_NAMESPACE_END diff --git a/ice40/cells.h b/ice40/cells.h index 1fa85413..1c2e0d0f 100644 --- a/ice40/cells.h +++ b/ice40/cells.h @@ -22,6 +22,8 @@ #ifndef ICE40_CELLS_H #define ICE40_CELLS_H +NEXTPNR_NAMESPACE_BEGIN + // Create a standard iCE40 cell and return it // Name will be automatically assigned if not specified CellInfo *create_ice_cell(Design *design, IdString type, @@ -51,4 +53,6 @@ inline bool is_ff(const CellInfo *cell) // ignored void dff_to_lc(CellInfo *dff, CellInfo *lc, bool pass_thru_lut = false); +NEXTPNR_NAMESPACE_END + #endif diff --git a/ice40/chip.cc b/ice40/chip.cc index 42252fa0..29da5644 100644 --- a/ice40/chip.cc +++ b/ice40/chip.cc @@ -20,6 +20,8 @@ #include "log.h" #include "nextpnr.h" +NEXTPNR_NAMESPACE_BEGIN + // ----------------------------------------------------------------------- IdString belTypeToId(BelType type) @@ -327,3 +329,5 @@ std::vector Chip::getFrameGraphics() const return ret; } + +NEXTPNR_NAMESPACE_END diff --git a/ice40/chip.h b/ice40/chip.h index 451be9ce..9dc0498c 100644 --- a/ice40/chip.h +++ b/ice40/chip.h @@ -24,6 +24,8 @@ #error Include "chip.h" via "nextpnr.h" only. #endif +NEXTPNR_NAMESPACE_BEGIN + struct DelayInfo { float delay = 0; @@ -210,32 +212,36 @@ struct BelPin PortPin pin; }; +NEXTPNR_NAMESPACE_END + namespace std { -template <> struct hash +template <> struct hash { - std::size_t operator()(const BelId &bel) const noexcept + std::size_t operator()(const NEXTPNR_NAMESPACE::BelId &bel) const noexcept { return bel.index; } }; -template <> struct hash +template <> struct hash { - std::size_t operator()(const WireId &wire) const noexcept + std::size_t operator()(const NEXTPNR_NAMESPACE::WireId &wire) const noexcept { return wire.index; } }; -template <> struct hash +template <> struct hash { - std::size_t operator()(const PipId &wire) const noexcept + std::size_t operator()(const NEXTPNR_NAMESPACE::PipId &wire) const noexcept { return wire.index; } }; } // namespace std +NEXTPNR_NAMESPACE_BEGIN + // ----------------------------------------------------------------------- struct BelIterator @@ -677,4 +683,6 @@ struct Chip std::vector getFrameGraphics() const; }; +NEXTPNR_NAMESPACE_END + #endif diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 34366679..9b246f8b 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -312,6 +312,8 @@ elif dev_name == "5k": add_bel_gb(19, 0, 7) print('#include "nextpnr.h"') +print('namespace {') +print('USING_NEXTPNR_NAMESPACE') for bel in range(len(bel_name)): print("static BelWirePOD bel_wires_%d[%d] = {" % (bel, len(bel_wires[bel]))) @@ -319,7 +321,7 @@ for bel in range(len(bel_name)): print(" {%d, PIN_%s}%s" % (bel_wires[bel][i] + ("," if i+1 < len(bel_wires[bel]) else "",))) print("};") -print("BelInfoPOD bel_data_%s[%d] = {" % (dev_name, len(bel_name))) +print("static BelInfoPOD bel_data_%s[%d] = {" % (dev_name, len(bel_name))) for bel in range(len(bel_name)): print(" {\"%s\", TYPE_%s, %d, bel_wires_%d, %d, %d, %d}%s" % (bel_name[bel], bel_type[bel], len(bel_wires[bel]), bel, bel_pos[bel][0], bel_pos[bel][1], bel_pos[bel][2], @@ -458,8 +460,13 @@ print("static TileType tile_grid_%s[%d] = {" % (dev_name, len(tilegrid))) print(",\n".join(tilegrid)) print("};") +print('}') +print('NEXTPNR_NAMESPACE_BEGIN') + print("ChipInfoPOD chip_info_%s = {" % dev_name) print(" %d, %d, %d, %d, %d, %d," % (dev_width, dev_height, len(bel_name), num_wires, len(pipinfo), len(switchinfo))) print(" bel_data_%s, wire_data_%s, pip_data_%s," % (dev_name, dev_name, dev_name)) print(" tile_grid_%s, &bits_info_%s" % (dev_name, dev_name)) print("};") + +print('NEXTPNR_NAMESPACE_END') diff --git a/ice40/family.cmake b/ice40/family.cmake index 33c5c20e..1ed2ecf3 100644 --- a/ice40/family.cmake +++ b/ice40/family.cmake @@ -11,6 +11,7 @@ set(DB_PY ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdb.py) file(MAKE_DIRECTORY ice40/chipdbs/) add_library(ice40_chipdb OBJECT ice40/chipdbs/) target_compile_options(ice40_chipdb PRIVATE -g0 -O0 -w) +target_compile_definitions(ice40_chipdb PRIVATE NEXTPNR_NAMESPACE=nextpnr_${family}) target_include_directories(ice40_chipdb PRIVATE ${family}/) foreach (dev ${devices}) set(DEV_TXT_DB /usr/local/share/icebox/chipdb-${dev}.txt) diff --git a/ice40/pybindings.cc b/ice40/pybindings.cc index c00bf6b9..9094fe7c 100644 --- a/ice40/pybindings.cc +++ b/ice40/pybindings.cc @@ -21,6 +21,8 @@ #include "pybindings.h" #include "nextpnr.h" +NEXTPNR_NAMESPACE_BEGIN + void arch_wrap_python() { class_("ChipArgs").def_readwrite("type", &ChipArgs::type); @@ -80,3 +82,5 @@ void arch_wrap_python() WRAP_RANGE(AllPip); WRAP_RANGE(Pip); } + +NEXTPNR_NAMESPACE_END -- cgit v1.2.3