From ad5f6fccaa4484eb02d3fa6d420ff39517b524e6 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 17 Mar 2023 18:58:04 +0100 Subject: Use RelSlice, make more in line with ecp5 arch --- machxo2/arch.h | 129 ++++++++++++++++++++++++++------------------------------- 1 file changed, 58 insertions(+), 71 deletions(-) (limited to 'machxo2/arch.h') diff --git a/machxo2/arch.h b/machxo2/arch.h index efb5ee41..8cb8accc 100644 --- a/machxo2/arch.h +++ b/machxo2/arch.h @@ -39,20 +39,14 @@ NPNR_PACKED_STRUCT(struct BelWirePOD { LocationPOD rel_wire_loc; int32_t wire_index; int32_t port; - int32_t dir; // FIXME: Corresponds to "type" in ECP5. + int32_t type; }); NPNR_PACKED_STRUCT(struct BelInfoPOD { RelPtr name; int32_t type; int32_t z; - int32_t num_bel_wires; - RelPtr bel_wires; -}); - -NPNR_PACKED_STRUCT(struct PipLocatorPOD { - LocationPOD rel_loc; - int32_t index; + RelSlice bel_wires; }); NPNR_PACKED_STRUCT(struct BelPortPOD { @@ -62,35 +56,39 @@ NPNR_PACKED_STRUCT(struct BelPortPOD { }); NPNR_PACKED_STRUCT(struct PipInfoPOD { - LocationPOD src; - LocationPOD dst; - int32_t src_idx; - int32_t dst_idx; + LocationPOD src, dst; + int32_t src_idx, dst_idx; int32_t timing_class; int16_t tile_type; int8_t pip_type; int8_t padding; }); +NPNR_PACKED_STRUCT(struct PipLocatorPOD { + LocationPOD rel_loc; + int32_t index; +}); + NPNR_PACKED_STRUCT(struct WireInfoPOD { RelPtr name; int16_t type; int16_t tile_wire; - int32_t num_uphill; - int32_t num_downhill; - RelPtr pips_uphill; - RelPtr pips_downhill; - int32_t num_bel_pins; - RelPtr bel_pins; + RelSlice pips_uphill, pips_downhill; + RelSlice bel_pins; }); NPNR_PACKED_STRUCT(struct TileTypePOD { - int32_t num_bels; - int32_t num_wires; - int32_t num_pips; - RelPtr bel_data; - RelPtr wire_data; - RelPtr pips_data; + RelSlice bel_data; + RelSlice wire_data; + RelSlice pip_data; +}); + +NPNR_PACKED_STRUCT(struct PIOInfoPOD { + LocationPOD abs_loc; + int32_t bel_index; + RelPtr function_name; + int16_t bank; + int16_t dqsgroup; }); NPNR_PACKED_STRUCT(struct PackagePinPOD { @@ -101,16 +99,7 @@ NPNR_PACKED_STRUCT(struct PackagePinPOD { NPNR_PACKED_STRUCT(struct PackageInfoPOD { RelPtr name; - int32_t num_pins; - RelPtr pin_data; -}); - -NPNR_PACKED_STRUCT(struct PIOInfoPOD { - LocationPOD abs_loc; - int32_t bel_index; - RelPtr function_name; - int16_t bank; - int16_t dqsgroup; + RelSlice pin_data; }); NPNR_PACKED_STRUCT(struct TileNamePOD { @@ -119,10 +108,7 @@ NPNR_PACKED_STRUCT(struct TileNamePOD { int16_t padding; }); -NPNR_PACKED_STRUCT(struct TileInfoPOD { - int32_t num_tiles; - RelPtr tile_names; -}); +NPNR_PACKED_STRUCT(struct TileInfoPOD { RelSlice tile_names; }); NPNR_PACKED_STRUCT(struct PackageSupportedPOD { RelPtr name; @@ -145,13 +131,12 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD { RelPtr device_name; int32_t width, height; int32_t num_tiles; - int32_t num_packages, num_pios; int32_t const_id_count; - RelPtr tiles; - RelPtr> tiletype_names; - RelPtr package_info; - RelPtr pio_info; - RelPtr tile_info; + RelSlice tiles; + RelSlice> tiletype_names; + RelSlice package_info; + RelSlice pio_info; + RelSlice tile_info; RelSlice variants; }); @@ -168,7 +153,7 @@ struct BelIterator BelIterator operator++() { cursor_index++; - while (cursor_tile < chip->num_tiles && cursor_index >= chip->tiles[cursor_tile].num_bels) { + while (cursor_tile < chip->num_tiles && cursor_index >= chip->tiles[cursor_tile].bel_data.ssize()) { cursor_index = 0; cursor_tile++; } @@ -243,7 +228,7 @@ struct WireIterator WireIterator operator++() { cursor_index++; - while (cursor_tile < chip->num_tiles && cursor_index >= chip->tiles[cursor_tile].num_wires) { + while (cursor_tile < chip->num_tiles && cursor_index >= chip->tiles[cursor_tile].wire_data.ssize()) { cursor_index = 0; cursor_tile++; } @@ -293,7 +278,7 @@ struct AllPipIterator AllPipIterator operator++() { cursor_index++; - while (cursor_tile < chip->num_tiles && cursor_index >= chip->tiles[cursor_tile].num_pips) { + while (cursor_tile < chip->num_tiles && cursor_index >= chip->tiles[cursor_tile].pip_data.ssize()) { cursor_index = 0; cursor_tile++; } @@ -518,13 +503,15 @@ struct Arch : BaseArch { BelPinRange range; NPNR_ASSERT(wire != WireId()); - range.b.ptr = tile_info(wire)->wire_data[wire.index].bel_pins.get(); + range.b.ptr = tile_info(wire)->wire_data[wire.index].bel_pins.begin(); range.b.wire_loc = wire.location; - range.e.ptr = range.b.ptr + tile_info(wire)->wire_data[wire.index].num_bel_pins; + range.e.ptr = tile_info(wire)->wire_data[wire.index].bel_pins.end(); range.e.wire_loc = wire.location; return range; } + IdString get_wire_basename(WireId wire) const { return id(tile_info(wire)->wire_data[wire.index].name.get()); } + // Pips PipId getPipByName(IdStringList name) const override; IdStringList getPipName(PipId pip) const override; @@ -558,8 +545,8 @@ struct Arch : BaseArch { WireId wire; NPNR_ASSERT(pip != PipId()); - wire.index = tile_info(pip)->pips_data[pip.index].src_idx; - wire.location = tile_info(pip)->pips_data[pip.index].src; + wire.index = tile_info(pip)->pip_data[pip.index].src_idx; + wire.location = tile_info(pip)->pip_data[pip.index].src; return wire; } @@ -567,8 +554,8 @@ struct Arch : BaseArch { WireId wire; NPNR_ASSERT(pip != PipId()); - wire.index = tile_info(pip)->pips_data[pip.index].dst_idx; - wire.location = tile_info(pip)->pips_data[pip.index].dst; + wire.index = tile_info(pip)->pip_data[pip.index].dst_idx; + wire.location = tile_info(pip)->pip_data[pip.index].dst; return wire; } @@ -580,7 +567,7 @@ struct Arch : BaseArch NPNR_ASSERT(wire != WireId()); range.b.cursor = tile_info(wire)->wire_data[wire.index].pips_downhill.get(); range.b.wire_loc = wire.location; - range.e.cursor = range.b.cursor + tile_info(wire)->wire_data[wire.index].num_downhill; + range.e.cursor = range.b.cursor + tile_info(wire)->wire_data[wire.index].pips_downhill.size(); range.e.wire_loc = wire.location; return range; } @@ -591,20 +578,20 @@ struct Arch : BaseArch NPNR_ASSERT(wire != WireId()); range.b.cursor = tile_info(wire)->wire_data[wire.index].pips_uphill.get(); range.b.wire_loc = wire.location; - range.e.cursor = range.b.cursor + tile_info(wire)->wire_data[wire.index].num_uphill; + range.e.cursor = range.b.cursor + tile_info(wire)->wire_data[wire.index].pips_uphill.size(); range.e.wire_loc = wire.location; return range; } // Extra Pip helpers. - int8_t get_pip_class(PipId pip) const { return tile_info(pip)->pips_data[pip.index].pip_type; } + int8_t get_pip_class(PipId pip) const { return tile_info(pip)->pip_data[pip.index].pip_type; } std::string get_pip_tilename(PipId pip) const { auto &tileloc = chip_info->tile_info[pip.location.y * chip_info->width + pip.location.x]; - for (int i = 0; i < tileloc.num_tiles; i++) { - if (tileloc.tile_names[i].type_idx == tile_info(pip)->pips_data[pip.index].tile_type) - return tileloc.tile_names[i].name.get(); + for (auto &tn : tileloc.tile_names) { + if (tn.type_idx == tile_info(pip)->pip_data[pip.index].tile_type) + return tn.name.get(); } NPNR_ASSERT_FALSE("failed to find Pip tile"); } @@ -646,24 +633,24 @@ struct Arch : BaseArch // Internal usage bool cells_compatible(const CellInfo **cells, int count) const; - std::vector> get_tiles_at_location(int row, int col); - std::string get_tile_by_type_and_loc(int row, int col, std::string type) const + std::vector> get_tiles_at_loc(int row, int col); + std::string get_tile_by_type_loc(int row, int col, std::string type) const { auto &tileloc = chip_info->tile_info[row * chip_info->width + col]; - for (int i = 0; i < tileloc.num_tiles; i++) { - if (chip_info->tiletype_names[tileloc.tile_names[i].type_idx].get() == type) - return tileloc.tile_names[i].name.get(); + for (auto &tn : tileloc.tile_names) { + if (chip_info->tiletype_names[tn.type_idx].get() == type) + return tn.name.get(); } NPNR_ASSERT_FALSE_STR("no tile at (" + std::to_string(col) + ", " + std::to_string(row) + ") with type " + type); } - std::string get_tile_by_type_and_loc(int row, int col, const std::set &type) const + std::string get_tile_by_type_loc(int row, int col, const std::set &type) const { auto &tileloc = chip_info->tile_info[row * chip_info->width + col]; - for (int i = 0; i < tileloc.num_tiles; i++) { - if (type.count(chip_info->tiletype_names[tileloc.tile_names[i].type_idx].get())) - return tileloc.tile_names[i].name.get(); + for (auto &tn : tileloc.tile_names) { + if (type.count(chip_info->tiletype_names[tn.type_idx].get())) + return tn.name.get(); } NPNR_ASSERT_FALSE_STR("no tile at (" + std::to_string(col) + ", " + std::to_string(row) + ") with type in set"); } @@ -672,9 +659,9 @@ struct Arch : BaseArch { for (int i = 0; i < chip_info->height * chip_info->width; i++) { auto &tileloc = chip_info->tile_info[i]; - for (int j = 0; j < tileloc.num_tiles; j++) - if (chip_info->tiletype_names[tileloc.tile_names[j].type_idx].get() == type) - return tileloc.tile_names[j].name.get(); + for (auto &tn : tileloc.tile_names) + if (chip_info->tiletype_names[tn.type_idx].get() == type) + return tn.name.get(); } NPNR_ASSERT_FALSE_STR("no tile with type " + type); } -- cgit v1.2.3