From 510969ab9704865f87c7c0bd09e0185b729feffc Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 11 Feb 2021 11:10:32 +0000
Subject: Create machxo2 backend (renamed from generic).

Signed-off-by: William D. Jones <thor0505@comcast.net>
---
 machxo2/examples/.gitignore       |  6 +++
 machxo2/examples/README.md        | 15 ++++++++
 machxo2/examples/__init__.py      |  0
 machxo2/examples/bitstream.py     | 17 +++++++++
 machxo2/examples/blinky.v         | 12 ++++++
 machxo2/examples/blinky_tb.v      | 38 +++++++++++++++++++
 machxo2/examples/simple.py        | 77 +++++++++++++++++++++++++++++++++++++++
 machxo2/examples/simple.sh        |  5 +++
 machxo2/examples/simple_config.py | 15 ++++++++
 machxo2/examples/simple_timing.py | 13 +++++++
 machxo2/examples/simtest.sh       |  7 ++++
 machxo2/examples/write_fasm.py    | 51 ++++++++++++++++++++++++++
 12 files changed, 256 insertions(+)
 create mode 100644 machxo2/examples/.gitignore
 create mode 100644 machxo2/examples/README.md
 create mode 100644 machxo2/examples/__init__.py
 create mode 100644 machxo2/examples/bitstream.py
 create mode 100644 machxo2/examples/blinky.v
 create mode 100644 machxo2/examples/blinky_tb.v
 create mode 100644 machxo2/examples/simple.py
 create mode 100644 machxo2/examples/simple.sh
 create mode 100644 machxo2/examples/simple_config.py
 create mode 100644 machxo2/examples/simple_timing.py
 create mode 100644 machxo2/examples/simtest.sh
 create mode 100644 machxo2/examples/write_fasm.py

(limited to 'machxo2/examples')

diff --git a/machxo2/examples/.gitignore b/machxo2/examples/.gitignore
new file mode 100644
index 00000000..ad2fba28
--- /dev/null
+++ b/machxo2/examples/.gitignore
@@ -0,0 +1,6 @@
+blinky.fasm
+__pycache__
+*.pyc
+pnrblinky.v
+/blinky_simtest
+*.vcd
diff --git a/machxo2/examples/README.md b/machxo2/examples/README.md
new file mode 100644
index 00000000..e064d077
--- /dev/null
+++ b/machxo2/examples/README.md
@@ -0,0 +1,15 @@
+# MachXO2 Architecture Example
+
+This contains a simple example of the nextpnr machxo2 API. As time goes on,
+python scripts required as boilerplate will be removed.
+
+ - simple.py procedurally generates a simple FPGA architecture with IO at the edges,
+   logic slices in all other tiles, and interconnect only between adjacent tiles
+
+ - simple_timing.py annotates cells with timing data (this is a separate script that must be run after packing)
+
+ - write_fasm.py uses the nextpnr Python API to write a FASM file for a design
+
+ - bitstream.py uses write_fasm.py to create a FASM ("FPGA assembly") file for the place-and-routed design
+
+ - Run simple.sh to build an example design on the FPGA above
diff --git a/machxo2/examples/__init__.py b/machxo2/examples/__init__.py
new file mode 100644
index 00000000..e69de29b
diff --git a/machxo2/examples/bitstream.py b/machxo2/examples/bitstream.py
new file mode 100644
index 00000000..7f0b5c07
--- /dev/null
+++ b/machxo2/examples/bitstream.py
@@ -0,0 +1,17 @@
+from write_fasm import *
+from simple_config import K
+
+# Need to tell FASM generator how to write parameters
+# (celltype, parameter) -> ParameterConfig
+param_map = {
+	("GENERIC_SLICE", "K"): ParameterConfig(write=False),
+	("GENERIC_SLICE", "INIT"): ParameterConfig(write=True, numeric=True, width=2**K),
+	("GENERIC_SLICE", "FF_USED"): ParameterConfig(write=True, numeric=True, width=1),
+
+	("GENERIC_IOB", "INPUT_USED"): ParameterConfig(write=True, numeric=True, width=1),
+	("GENERIC_IOB", "OUTPUT_USED"): ParameterConfig(write=True, numeric=True, width=1),
+	("GENERIC_IOB", "ENABLE_USED"): ParameterConfig(write=True, numeric=True, width=1),
+}
+
+with open("blinky.fasm", "w") as f:
+	write_fasm(ctx, param_map, f)
diff --git a/machxo2/examples/blinky.v b/machxo2/examples/blinky.v
new file mode 100644
index 00000000..42becb72
--- /dev/null
+++ b/machxo2/examples/blinky.v
@@ -0,0 +1,12 @@
+module top(input clk, rst, output reg [7:0] leds);
+
+reg [7:0] ctr;
+always @(posedge clk)
+	if (rst)
+		ctr <= 8'h00;
+	else
+		ctr <= ctr + 1'b1;
+
+assign leds = ctr;
+
+endmodule
diff --git a/machxo2/examples/blinky_tb.v b/machxo2/examples/blinky_tb.v
new file mode 100644
index 00000000..f9925e6f
--- /dev/null
+++ b/machxo2/examples/blinky_tb.v
@@ -0,0 +1,38 @@
+`timescale 1ns / 1ps
+module blinky_tb;
+
+reg clk = 1'b0, rst = 1'b0;
+reg [7:0] ctr_gold = 8'h00;
+wire [7:0] ctr_gate;
+top dut_i(.clk(clk), .rst(rst), .leds(ctr_gate));
+
+task oneclk;
+	begin
+		clk = 1'b1;
+		#10;
+		clk = 1'b0;
+		#10;
+	end
+endtask
+
+initial begin
+	$dumpfile("blinky_simtest.vcd");
+	$dumpvars(0, blinky_tb);
+	#100;
+	rst = 1'b1;
+	repeat (5) oneclk;
+	#5
+	rst = 1'b0;
+	#5
+	repeat (500) begin
+		if (ctr_gold !== ctr_gate) begin
+			$display("mismatch gold=%b gate=%b", ctr_gold, ctr_gate);
+			$stop;
+		end
+		oneclk;
+		ctr_gold = ctr_gold + 1'b1;
+	end
+	$finish;
+end
+
+endmodule
diff --git a/machxo2/examples/simple.py b/machxo2/examples/simple.py
new file mode 100644
index 00000000..9379b505
--- /dev/null
+++ b/machxo2/examples/simple.py
@@ -0,0 +1,77 @@
+from simple_config import *
+
+def is_io(x, y):
+	return x == 0 or x == X-1 or y == 0 or y == Y-1
+
+for x in range(X):
+	for y in range(Y):
+		# Bel port wires
+		for z in range(N):
+			ctx.addWire(name="X%dY%dZ%d_CLK" % (x, y, z), type="BEL_CLK", x=x, y=y)
+			ctx.addWire(name="X%dY%dZ%d_Q" % (x, y, z), type="BEL_Q", x=x, y=y)
+			ctx.addWire(name="X%dY%dZ%d_F" % (x, y, z), type="BEL_F", x=x, y=y)
+			for i in range(K):
+				ctx.addWire(name="X%dY%dZ%d_I%d" % (x, y, z, i), type="BEL_I", x=x, y=y)
+		# Local wires
+		for l in range(Wl):
+			ctx.addWire(name="X%dY%d_LOCAL%d" % (x, y, l), type="LOCAL", x=x, y=y)
+		# Create bels
+		if is_io(x, y):
+			if x == y:
+				continue
+			for z in range(2):
+				ctx.addBel(name="X%dY%d_IO%d" % (x, y, z), type="GENERIC_IOB", loc=Loc(x, y, z), gb=False)
+				ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="I", wire="X%dY%dZ%d_I0" % (x, y, z))
+				ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="EN", wire="X%dY%dZ%d_I1" % (x, y, z))
+				ctx.addBelOutput(bel="X%dY%d_IO%d" % (x, y, z), name="O", wire="X%dY%dZ%d_Q" % (x, y, z))
+		else:
+			for z in range(N):
+				ctx.addBel(name="X%dY%d_SLICE%d" % (x, y, z), type="GENERIC_SLICE", loc=Loc(x, y, z), gb=False)
+				ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="CLK", wire="X%dY%dZ%d_CLK" % (x, y, z))
+				for k in range(K):
+					ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="I[%d]" % k, wire="X%dY%dZ%d_I%d" % (x, y, z, k))
+				ctx.addBelOutput(bel="X%dY%d_SLICE%d" % (x, y, z), name="F", wire="X%dY%dZ%d_F" % (x, y, z))
+				ctx.addBelOutput(bel="X%dY%d_SLICE%d" % (x, y, z), name="Q", wire="X%dY%dZ%d_Q" % (x, y, z))
+
+for x in range(X):
+	for y in range(Y):
+		# Pips driving bel input wires
+		# Bel input wires are driven by every Si'th local with an offset
+		def create_input_pips(dst, offset, skip):
+			for i in range(offset % skip, Wl, skip):
+				src = "X%dY%d_LOCAL%d" % (x, y, i)
+				ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="BEL_INPUT",
+					srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0))
+		for z in range(N):
+			create_input_pips("X%dY%dZ%d_CLK" % (x, y, z), 0, Si)
+			for k in range(K):
+				create_input_pips("X%dY%dZ%d_I%d" % (x, y, z, k), k % Si, Si)
+
+		# Pips from bel outputs to locals
+		def create_output_pips(dst, offset, skip):
+			for i in range(offset % skip, N, skip):
+				src = "X%dY%dZ%d_F" % (x, y, i)
+				ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="BEL_OUTPUT",
+					srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0))
+				src = "X%dY%dZ%d_Q" % (x, y, i)
+				ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="BEL_OUTPUT",
+					srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0))
+		# Pips from neighbour locals to locals
+		def create_neighbour_pips(dst, nx, ny, offset, skip):
+			if nx < 0 or nx >= X or ny < 0 or ny >= Y:
+				return
+			for i in range(offset % skip, Wl, skip):
+				src = "X%dY%d_LOCAL%d" % (nx, ny, i)
+				ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="NEIGHBOUR",
+					srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0))
+		for l in range(Wl):
+			dst = "X%dY%d_LOCAL%d" % (x, y, l)
+			create_output_pips(dst, l % Sq, Sq)
+			create_neighbour_pips(dst, x-1, y-1, (l + 1) % Sl, Sl)
+			create_neighbour_pips(dst, x-1, y, (l + 2) % Sl, Sl)
+			create_neighbour_pips(dst, x-1, y+1, (l + 2) % Sl, Sl)
+			create_neighbour_pips(dst, x, y-1, (l + 3) % Sl, Sl)
+			create_neighbour_pips(dst, x, y+1, (l + 4) % Sl, Sl)
+			create_neighbour_pips(dst, x+1, y-1, (l + 5) % Sl, Sl)
+			create_neighbour_pips(dst, x+1, y, (l + 6) % Sl, Sl)
+			create_neighbour_pips(dst, x+1, y+1, (l + 7) % Sl, Sl)
diff --git a/machxo2/examples/simple.sh b/machxo2/examples/simple.sh
new file mode 100644
index 00000000..425bc6ff
--- /dev/null
+++ b/machxo2/examples/simple.sh
@@ -0,0 +1,5 @@
+#!/usr/bin/env bash
+set -ex
+yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v
+${NEXTPNR:-../../nextpnr-machxo2} --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route bitstream.py --write pnrblinky.json
+yosys -p "read_verilog -lib ../synth/prims.v; read_json pnrblinky.json; dump -o blinky.il; show -format png -prefix blinky"
diff --git a/machxo2/examples/simple_config.py b/machxo2/examples/simple_config.py
new file mode 100644
index 00000000..dfb38f1c
--- /dev/null
+++ b/machxo2/examples/simple_config.py
@@ -0,0 +1,15 @@
+# Grid size including IOBs at edges
+X = 12
+Y = 12
+# SLICEs per tile
+N = 8
+# LUT input count
+K = 4
+# Number of local wires
+Wl = N*(K+1) + 8 
+# 1/Fc for bel input wire pips
+Si = 4
+# 1/Fc for Q to local wire pips
+Sq = 4
+# ~1/Fc local to neighbour local wire pips
+Sl = 8
\ No newline at end of file
diff --git a/machxo2/examples/simple_timing.py b/machxo2/examples/simple_timing.py
new file mode 100644
index 00000000..1067b556
--- /dev/null
+++ b/machxo2/examples/simple_timing.py
@@ -0,0 +1,13 @@
+for cname, cell in ctx.cells:
+    if cell.type != "GENERIC_SLICE":
+        continue
+    if cname in ("$PACKER_GND", "$PACKER_VCC"):
+        continue
+    K = int(cell.params["K"])
+    ctx.addCellTimingClock(cell=cname, port="CLK")
+    for i in range(K):
+        ctx.addCellTimingSetupHold(cell=cname, port="I[%d]" % i, clock="CLK",
+            setup=ctx.getDelayFromNS(0.2), hold=ctx.getDelayFromNS(0))
+    ctx.addCellTimingClockToOut(cell=cname, port="Q", clock="CLK", clktoq=ctx.getDelayFromNS(0.2))
+    for i in range(K):
+        ctx.addCellTimingDelay(cell=cname, fromPort="I[%d]" % i, toPort="F", delay=ctx.getDelayFromNS(0.2))
diff --git a/machxo2/examples/simtest.sh b/machxo2/examples/simtest.sh
new file mode 100644
index 00000000..a53f5c15
--- /dev/null
+++ b/machxo2/examples/simtest.sh
@@ -0,0 +1,7 @@
+#!/usr/bin/env bash
+set -ex
+yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v
+${NEXTPNR:-../../nextpnr-machxo2} --no-iobs --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route bitstream.py --write pnrblinky.json
+yosys -p "read_json pnrblinky.json; write_verilog -noattr -norename pnrblinky.v"
+iverilog -o blinky_simtest ../synth/prims.v blinky_tb.v pnrblinky.v
+vvp -N ./blinky_simtest
diff --git a/machxo2/examples/write_fasm.py b/machxo2/examples/write_fasm.py
new file mode 100644
index 00000000..ede8f16b
--- /dev/null
+++ b/machxo2/examples/write_fasm.py
@@ -0,0 +1,51 @@
+from collections import namedtuple
+
+"""
+	write:   set to True to enable writing this parameter to FASM
+
+	numeric: set to True to write this parameter as a bit array (width>1) or
+	         single bit (width==1) named after the parameter. Otherwise this
+	         parameter will be written as `name.value`
+
+	width:   width of numeric parameter (ignored for non-numeric parameters)
+	
+	alias:   an alternative name for this parameter (parameter name used if alias
+	         is None)
+"""
+ParameterConfig = namedtuple('ParameterConfig', 'write numeric width alias')
+
+# FIXME use defaults= once Python 3.7 is standard
+ParameterConfig.__new__.__defaults__ = (False, True, 1, None)
+
+
+"""
+Write a design as FASM
+
+    ctx:      nextpnr context
+    paramCfg: map from (celltype, parametername) -> ParameterConfig describing how to write parameters
+    f:        output file
+"""
+def write_fasm(ctx, paramCfg, f):
+	for nname, net in sorted(ctx.nets, key=lambda x: str(x[1].name)):
+		print("# Net %s" % nname, file=f)
+		for wire, pip in sorted(net.wires, key=lambda x: str(x[1])):
+			if pip.pip != "":
+				print("%s" % pip.pip, file=f)
+		print("", file=f)
+	for cname, cell in sorted(ctx.cells, key=lambda x: str(x[1].name)):
+		print("# Cell %s at %s" % (cname, cell.bel), file=f)
+		for param, val in sorted(cell.params, key=lambda x: str(x)):
+			cfg = paramCfg[(cell.type, param)]
+			if not cfg.write:
+				continue
+			fasm_name = cfg.alias if cfg.alias is not None else param
+			if cfg.numeric:
+				if cfg.width == 1:
+					if int(val) != 0:
+						print("%s.%s" % (cell.bel, fasm_name), file=f)
+				else:
+					# Parameters with width >32 are direct binary, otherwise denary
+					print("%s.%s[%d:0] = %d'b%s" % (cell.bel, fasm_name, cfg.width-1, cfg.width, val), file=f)
+			else:
+				print("%s.%s.%s" % (cell.bel, fasm_name, val), file=f)
+		print("", file=f)
\ No newline at end of file
-- 
cgit v1.2.3


From 78880e1fdf1721a460c7e4e813f91f427106d3b7 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Sat, 27 Jun 2020 17:40:35 -0400
Subject: machxo2: Remove pybindings unneeded files from examples and update
 README.md and scripts accordingly. Delete resources directory.

---
 machxo2/examples/.gitignore       |  4 +-
 machxo2/examples/README.md        | 23 ++++++------
 machxo2/examples/__init__.py      |  0
 machxo2/examples/bitstream.py     | 17 ---------
 machxo2/examples/simple.py        | 77 ---------------------------------------
 machxo2/examples/simple.sh        |  4 +-
 machxo2/examples/simple_config.py | 15 --------
 machxo2/examples/simple_timing.py | 13 -------
 machxo2/examples/simtest.sh       |  4 +-
 machxo2/examples/write_fasm.py    | 51 --------------------------
 10 files changed, 17 insertions(+), 191 deletions(-)
 delete mode 100644 machxo2/examples/__init__.py
 delete mode 100644 machxo2/examples/bitstream.py
 delete mode 100644 machxo2/examples/simple.py
 delete mode 100644 machxo2/examples/simple_config.py
 delete mode 100644 machxo2/examples/simple_timing.py
 delete mode 100644 machxo2/examples/write_fasm.py

(limited to 'machxo2/examples')

diff --git a/machxo2/examples/.gitignore b/machxo2/examples/.gitignore
index ad2fba28..f1ee6a8a 100644
--- a/machxo2/examples/.gitignore
+++ b/machxo2/examples/.gitignore
@@ -1,6 +1,4 @@
-blinky.fasm
-__pycache__
-*.pyc
 pnrblinky.v
 /blinky_simtest
 *.vcd
+abc.history
diff --git a/machxo2/examples/README.md b/machxo2/examples/README.md
index e064d077..f82da63a 100644
--- a/machxo2/examples/README.md
+++ b/machxo2/examples/README.md
@@ -1,15 +1,16 @@
 # MachXO2 Architecture Example
 
-This contains a simple example of the nextpnr machxo2 API. As time goes on,
-python scripts required as boilerplate will be removed.
+This contains a simple example of running `nextpnr-machxo2`:
 
- - simple.py procedurally generates a simple FPGA architecture with IO at the edges,
-   logic slices in all other tiles, and interconnect only between adjacent tiles
+* `simple.sh` generates JSON output (`pnrblinky.json`) of a classic blinky
+  example from `blinky.v`.
+* `simtest.sh` will use `yosys` to generate a Verilog file from
+  `pnrblinky.json`, called `pnrblinky.v`. It will then and compare
+  `pnrblinky.v`'s simulation behavior to the original verilog file (`blinky.v`)
+  using the [`iverilog`](http://iverilog.icarus.com) compiler and `vvp`
+  runtime. This is known as post-place-and-route simulation.
 
- - simple_timing.py annotates cells with timing data (this is a separate script that must be run after packing)
-
- - write_fasm.py uses the nextpnr Python API to write a FASM file for a design
-
- - bitstream.py uses write_fasm.py to create a FASM ("FPGA assembly") file for the place-and-routed design
-
- - Run simple.sh to build an example design on the FPGA above
+As `nextpnr-machxo2` is developed the `nextpnr` invocation in `simple.sh` and
+`simtest.sh` is subject to change. Other command invocations, such as `yosys`,
+_should_ remain unchanged, even as files under the [synth](../synth) directory
+change.
diff --git a/machxo2/examples/__init__.py b/machxo2/examples/__init__.py
deleted file mode 100644
index e69de29b..00000000
diff --git a/machxo2/examples/bitstream.py b/machxo2/examples/bitstream.py
deleted file mode 100644
index 7f0b5c07..00000000
--- a/machxo2/examples/bitstream.py
+++ /dev/null
@@ -1,17 +0,0 @@
-from write_fasm import *
-from simple_config import K
-
-# Need to tell FASM generator how to write parameters
-# (celltype, parameter) -> ParameterConfig
-param_map = {
-	("GENERIC_SLICE", "K"): ParameterConfig(write=False),
-	("GENERIC_SLICE", "INIT"): ParameterConfig(write=True, numeric=True, width=2**K),
-	("GENERIC_SLICE", "FF_USED"): ParameterConfig(write=True, numeric=True, width=1),
-
-	("GENERIC_IOB", "INPUT_USED"): ParameterConfig(write=True, numeric=True, width=1),
-	("GENERIC_IOB", "OUTPUT_USED"): ParameterConfig(write=True, numeric=True, width=1),
-	("GENERIC_IOB", "ENABLE_USED"): ParameterConfig(write=True, numeric=True, width=1),
-}
-
-with open("blinky.fasm", "w") as f:
-	write_fasm(ctx, param_map, f)
diff --git a/machxo2/examples/simple.py b/machxo2/examples/simple.py
deleted file mode 100644
index 9379b505..00000000
--- a/machxo2/examples/simple.py
+++ /dev/null
@@ -1,77 +0,0 @@
-from simple_config import *
-
-def is_io(x, y):
-	return x == 0 or x == X-1 or y == 0 or y == Y-1
-
-for x in range(X):
-	for y in range(Y):
-		# Bel port wires
-		for z in range(N):
-			ctx.addWire(name="X%dY%dZ%d_CLK" % (x, y, z), type="BEL_CLK", x=x, y=y)
-			ctx.addWire(name="X%dY%dZ%d_Q" % (x, y, z), type="BEL_Q", x=x, y=y)
-			ctx.addWire(name="X%dY%dZ%d_F" % (x, y, z), type="BEL_F", x=x, y=y)
-			for i in range(K):
-				ctx.addWire(name="X%dY%dZ%d_I%d" % (x, y, z, i), type="BEL_I", x=x, y=y)
-		# Local wires
-		for l in range(Wl):
-			ctx.addWire(name="X%dY%d_LOCAL%d" % (x, y, l), type="LOCAL", x=x, y=y)
-		# Create bels
-		if is_io(x, y):
-			if x == y:
-				continue
-			for z in range(2):
-				ctx.addBel(name="X%dY%d_IO%d" % (x, y, z), type="GENERIC_IOB", loc=Loc(x, y, z), gb=False)
-				ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="I", wire="X%dY%dZ%d_I0" % (x, y, z))
-				ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="EN", wire="X%dY%dZ%d_I1" % (x, y, z))
-				ctx.addBelOutput(bel="X%dY%d_IO%d" % (x, y, z), name="O", wire="X%dY%dZ%d_Q" % (x, y, z))
-		else:
-			for z in range(N):
-				ctx.addBel(name="X%dY%d_SLICE%d" % (x, y, z), type="GENERIC_SLICE", loc=Loc(x, y, z), gb=False)
-				ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="CLK", wire="X%dY%dZ%d_CLK" % (x, y, z))
-				for k in range(K):
-					ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="I[%d]" % k, wire="X%dY%dZ%d_I%d" % (x, y, z, k))
-				ctx.addBelOutput(bel="X%dY%d_SLICE%d" % (x, y, z), name="F", wire="X%dY%dZ%d_F" % (x, y, z))
-				ctx.addBelOutput(bel="X%dY%d_SLICE%d" % (x, y, z), name="Q", wire="X%dY%dZ%d_Q" % (x, y, z))
-
-for x in range(X):
-	for y in range(Y):
-		# Pips driving bel input wires
-		# Bel input wires are driven by every Si'th local with an offset
-		def create_input_pips(dst, offset, skip):
-			for i in range(offset % skip, Wl, skip):
-				src = "X%dY%d_LOCAL%d" % (x, y, i)
-				ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="BEL_INPUT",
-					srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0))
-		for z in range(N):
-			create_input_pips("X%dY%dZ%d_CLK" % (x, y, z), 0, Si)
-			for k in range(K):
-				create_input_pips("X%dY%dZ%d_I%d" % (x, y, z, k), k % Si, Si)
-
-		# Pips from bel outputs to locals
-		def create_output_pips(dst, offset, skip):
-			for i in range(offset % skip, N, skip):
-				src = "X%dY%dZ%d_F" % (x, y, i)
-				ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="BEL_OUTPUT",
-					srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0))
-				src = "X%dY%dZ%d_Q" % (x, y, i)
-				ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="BEL_OUTPUT",
-					srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0))
-		# Pips from neighbour locals to locals
-		def create_neighbour_pips(dst, nx, ny, offset, skip):
-			if nx < 0 or nx >= X or ny < 0 or ny >= Y:
-				return
-			for i in range(offset % skip, Wl, skip):
-				src = "X%dY%d_LOCAL%d" % (nx, ny, i)
-				ctx.addPip(name="X%dY%d.%s.%s" % (x, y, src, dst), type="NEIGHBOUR",
-					srcWire=src, dstWire=dst, delay=ctx.getDelayFromNS(0.05), loc=Loc(x, y, 0))
-		for l in range(Wl):
-			dst = "X%dY%d_LOCAL%d" % (x, y, l)
-			create_output_pips(dst, l % Sq, Sq)
-			create_neighbour_pips(dst, x-1, y-1, (l + 1) % Sl, Sl)
-			create_neighbour_pips(dst, x-1, y, (l + 2) % Sl, Sl)
-			create_neighbour_pips(dst, x-1, y+1, (l + 2) % Sl, Sl)
-			create_neighbour_pips(dst, x, y-1, (l + 3) % Sl, Sl)
-			create_neighbour_pips(dst, x, y+1, (l + 4) % Sl, Sl)
-			create_neighbour_pips(dst, x+1, y-1, (l + 5) % Sl, Sl)
-			create_neighbour_pips(dst, x+1, y, (l + 6) % Sl, Sl)
-			create_neighbour_pips(dst, x+1, y+1, (l + 7) % Sl, Sl)
diff --git a/machxo2/examples/simple.sh b/machxo2/examples/simple.sh
index 425bc6ff..7f973033 100644
--- a/machxo2/examples/simple.sh
+++ b/machxo2/examples/simple.sh
@@ -1,5 +1,5 @@
 #!/usr/bin/env bash
 set -ex
-yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v
-${NEXTPNR:-../../nextpnr-machxo2} --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route bitstream.py --write pnrblinky.json
+yosys -p "tcl ../synth/synth_machxo2.tcl 4 blinky.json" blinky.v
+${NEXTPNR:-../../nextpnr-machxo2} --json blinky.json --write pnrblinky.json
 yosys -p "read_verilog -lib ../synth/prims.v; read_json pnrblinky.json; dump -o blinky.il; show -format png -prefix blinky"
diff --git a/machxo2/examples/simple_config.py b/machxo2/examples/simple_config.py
deleted file mode 100644
index dfb38f1c..00000000
--- a/machxo2/examples/simple_config.py
+++ /dev/null
@@ -1,15 +0,0 @@
-# Grid size including IOBs at edges
-X = 12
-Y = 12
-# SLICEs per tile
-N = 8
-# LUT input count
-K = 4
-# Number of local wires
-Wl = N*(K+1) + 8 
-# 1/Fc for bel input wire pips
-Si = 4
-# 1/Fc for Q to local wire pips
-Sq = 4
-# ~1/Fc local to neighbour local wire pips
-Sl = 8
\ No newline at end of file
diff --git a/machxo2/examples/simple_timing.py b/machxo2/examples/simple_timing.py
deleted file mode 100644
index 1067b556..00000000
--- a/machxo2/examples/simple_timing.py
+++ /dev/null
@@ -1,13 +0,0 @@
-for cname, cell in ctx.cells:
-    if cell.type != "GENERIC_SLICE":
-        continue
-    if cname in ("$PACKER_GND", "$PACKER_VCC"):
-        continue
-    K = int(cell.params["K"])
-    ctx.addCellTimingClock(cell=cname, port="CLK")
-    for i in range(K):
-        ctx.addCellTimingSetupHold(cell=cname, port="I[%d]" % i, clock="CLK",
-            setup=ctx.getDelayFromNS(0.2), hold=ctx.getDelayFromNS(0))
-    ctx.addCellTimingClockToOut(cell=cname, port="Q", clock="CLK", clktoq=ctx.getDelayFromNS(0.2))
-    for i in range(K):
-        ctx.addCellTimingDelay(cell=cname, fromPort="I[%d]" % i, toPort="F", delay=ctx.getDelayFromNS(0.2))
diff --git a/machxo2/examples/simtest.sh b/machxo2/examples/simtest.sh
index a53f5c15..5e7d821d 100644
--- a/machxo2/examples/simtest.sh
+++ b/machxo2/examples/simtest.sh
@@ -1,7 +1,7 @@
 #!/usr/bin/env bash
 set -ex
-yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v
-${NEXTPNR:-../../nextpnr-machxo2} --no-iobs --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route bitstream.py --write pnrblinky.json
+yosys -p "tcl ../synth/synth_machxo2.tcl 4 blinky.json" blinky.v
+${NEXTPNR:-../../nextpnr-machxo2} --no-iobs --json blinky.json --write pnrblinky.json
 yosys -p "read_json pnrblinky.json; write_verilog -noattr -norename pnrblinky.v"
 iverilog -o blinky_simtest ../synth/prims.v blinky_tb.v pnrblinky.v
 vvp -N ./blinky_simtest
diff --git a/machxo2/examples/write_fasm.py b/machxo2/examples/write_fasm.py
deleted file mode 100644
index ede8f16b..00000000
--- a/machxo2/examples/write_fasm.py
+++ /dev/null
@@ -1,51 +0,0 @@
-from collections import namedtuple
-
-"""
-	write:   set to True to enable writing this parameter to FASM
-
-	numeric: set to True to write this parameter as a bit array (width>1) or
-	         single bit (width==1) named after the parameter. Otherwise this
-	         parameter will be written as `name.value`
-
-	width:   width of numeric parameter (ignored for non-numeric parameters)
-	
-	alias:   an alternative name for this parameter (parameter name used if alias
-	         is None)
-"""
-ParameterConfig = namedtuple('ParameterConfig', 'write numeric width alias')
-
-# FIXME use defaults= once Python 3.7 is standard
-ParameterConfig.__new__.__defaults__ = (False, True, 1, None)
-
-
-"""
-Write a design as FASM
-
-    ctx:      nextpnr context
-    paramCfg: map from (celltype, parametername) -> ParameterConfig describing how to write parameters
-    f:        output file
-"""
-def write_fasm(ctx, paramCfg, f):
-	for nname, net in sorted(ctx.nets, key=lambda x: str(x[1].name)):
-		print("# Net %s" % nname, file=f)
-		for wire, pip in sorted(net.wires, key=lambda x: str(x[1])):
-			if pip.pip != "":
-				print("%s" % pip.pip, file=f)
-		print("", file=f)
-	for cname, cell in sorted(ctx.cells, key=lambda x: str(x[1].name)):
-		print("# Cell %s at %s" % (cname, cell.bel), file=f)
-		for param, val in sorted(cell.params, key=lambda x: str(x)):
-			cfg = paramCfg[(cell.type, param)]
-			if not cfg.write:
-				continue
-			fasm_name = cfg.alias if cfg.alias is not None else param
-			if cfg.numeric:
-				if cfg.width == 1:
-					if int(val) != 0:
-						print("%s.%s" % (cell.bel, fasm_name), file=f)
-				else:
-					# Parameters with width >32 are direct binary, otherwise denary
-					print("%s.%s[%d:0] = %d'b%s" % (cell.bel, fasm_name, cfg.width-1, cfg.width, val), file=f)
-			else:
-				print("%s.%s.%s" % (cell.bel, fasm_name, val), file=f)
-		print("", file=f)
\ No newline at end of file
-- 
cgit v1.2.3


From 1cde40792f2d8cf8d0799fec25c0418a0903547f Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Sat, 21 Nov 2020 18:42:30 -0500
Subject: machxo2: Improve examples directory.

---
 machxo2/examples/README.md  | 21 +++++++++++++++++----
 machxo2/examples/blinky.v   |  2 +-
 machxo2/examples/simple.sh  |  4 ++--
 machxo2/examples/simtest.sh |  6 +++---
 4 files changed, 23 insertions(+), 10 deletions(-)

(limited to 'machxo2/examples')

diff --git a/machxo2/examples/README.md b/machxo2/examples/README.md
index f82da63a..87f50f6d 100644
--- a/machxo2/examples/README.md
+++ b/machxo2/examples/README.md
@@ -10,7 +10,20 @@ This contains a simple example of running `nextpnr-machxo2`:
   using the [`iverilog`](http://iverilog.icarus.com) compiler and `vvp`
   runtime. This is known as post-place-and-route simulation.
 
-As `nextpnr-machxo2` is developed the `nextpnr` invocation in `simple.sh` and
-`simtest.sh` is subject to change. Other command invocations, such as `yosys`,
-_should_ remain unchanged, even as files under the [synth](../synth) directory
-change.
+As `nextpnr-machxo2` is developed the contents `simple.sh` and `simtest.sh`
+are subject to change.
+
+## Environment Variables For `simple.sh` And `simtest.sh`
+
+* `YOSYS`- Set to the location of the `yosys` binary to test. Defaults to the
+  `yosys` on the path. You may want to set this to a `yosys` binary in your
+  source tree if doing development.
+* `NEXTPNR`- Set to the location of the `nextpnr-machxo2` binary to test.
+  Defaults to the `nextpnr-machxo2` binary at the root of the `nextpnr` source
+  tree. This should be set, for instance, if doing an out-of-tree build of
+  `nextpnr-machxo2`.
+* `CELLS_SIM`- Set to the location of `machxo2/cells_sim.v` simulation models.
+  Defaults to whatever `yosys-config` associated with the above `YOSYS` binary
+  returns. You may want to set this to `/path/to/yosys/src/share/machxo2/cells_sim.v`
+  if doing development; `yosys-config` cannot find these "before-installation"
+  simulation models.
diff --git a/machxo2/examples/blinky.v b/machxo2/examples/blinky.v
index 42becb72..c7cde26d 100644
--- a/machxo2/examples/blinky.v
+++ b/machxo2/examples/blinky.v
@@ -1,4 +1,4 @@
-module top(input clk, rst, output reg [7:0] leds);
+module top(input clk, rst, output [7:0] leds);
 
 reg [7:0] ctr;
 always @(posedge clk)
diff --git a/machxo2/examples/simple.sh b/machxo2/examples/simple.sh
index 7f973033..9eb06886 100644
--- a/machxo2/examples/simple.sh
+++ b/machxo2/examples/simple.sh
@@ -1,5 +1,5 @@
 #!/usr/bin/env bash
 set -ex
-yosys -p "tcl ../synth/synth_machxo2.tcl 4 blinky.json" blinky.v
+${YOSYS:yosys} -p "synth_machxo2 -json blinky.json" blinky.v
 ${NEXTPNR:-../../nextpnr-machxo2} --json blinky.json --write pnrblinky.json
-yosys -p "read_verilog -lib ../synth/prims.v; read_json pnrblinky.json; dump -o blinky.il; show -format png -prefix blinky"
+${YOSYS:yosys} -p "read_verilog -lib +/machxo2/cells_sim.v; read_json pnrblinky.json; dump -o blinky.il; show -format png -prefix blinky"
diff --git a/machxo2/examples/simtest.sh b/machxo2/examples/simtest.sh
index 5e7d821d..4cb8d5ca 100644
--- a/machxo2/examples/simtest.sh
+++ b/machxo2/examples/simtest.sh
@@ -1,7 +1,7 @@
 #!/usr/bin/env bash
 set -ex
-yosys -p "tcl ../synth/synth_machxo2.tcl 4 blinky.json" blinky.v
+${YOSYS:-yosys} -p "synth_machxo2 -json blinky.json" blinky.v
 ${NEXTPNR:-../../nextpnr-machxo2} --no-iobs --json blinky.json --write pnrblinky.json
-yosys -p "read_json pnrblinky.json; write_verilog -noattr -norename pnrblinky.v"
-iverilog -o blinky_simtest ../synth/prims.v blinky_tb.v pnrblinky.v
+${YOSYS:-yosys} -p "read_json blinky.json; write_verilog  -noattr -norename pnrblinky.v"
+iverilog -o blinky_simtest ${CELLS_SIM:-`${YOSYS:yosys}-config --datdir/machxo2/cells_sim.v`} blinky_tb.v pnrblinky.v
 vvp -N ./blinky_simtest
-- 
cgit v1.2.3


From 5838662b2f8a06aef52eac8218175f59547b5f09 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Thu, 26 Nov 2020 19:27:09 -0500
Subject: machxo2: Make sure REGSET FF parameter is set in FACADE_SLICE. Init
 blinky ctr to 0 for miter circuit.

---
 machxo2/examples/blinky.v | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'machxo2/examples')

diff --git a/machxo2/examples/blinky.v b/machxo2/examples/blinky.v
index c7cde26d..2137ad58 100644
--- a/machxo2/examples/blinky.v
+++ b/machxo2/examples/blinky.v
@@ -1,6 +1,7 @@
 module top(input clk, rst, output [7:0] leds);
 
-reg [7:0] ctr;
+// TODO: Test miter circuit without reset value.
+reg [7:0] ctr = 8'h00;
 always @(posedge clk)
 	if (rst)
 		ctr <= 8'h00;
-- 
cgit v1.2.3


From 4f042eac5338c789ad90ac10dc2a9d8e92ce1acd Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Sat, 28 Nov 2020 21:08:09 -0500
Subject: machxo2: Rework examples to test pack, place, and route phases.

---
 machxo2/examples/.gitignore   |  5 ++++-
 machxo2/examples/README.md    | 37 ++++++++++++++++++++++++++++---------
 machxo2/examples/blinky.v     |  6 +++++-
 machxo2/examples/mitertest.sh | 43 +++++++++++++++++++++++++++++++++++++++++++
 machxo2/examples/simple.sh    | 35 ++++++++++++++++++++++++++++++++---
 machxo2/examples/simtest.sh   | 37 +++++++++++++++++++++++++++++++++----
 6 files changed, 145 insertions(+), 18 deletions(-)
 create mode 100644 machxo2/examples/mitertest.sh

(limited to 'machxo2/examples')

diff --git a/machxo2/examples/.gitignore b/machxo2/examples/.gitignore
index f1ee6a8a..a4c8185f 100644
--- a/machxo2/examples/.gitignore
+++ b/machxo2/examples/.gitignore
@@ -1,4 +1,7 @@
-pnrblinky.v
 /blinky_simtest
 *.vcd
+*.png
+pack*.v
+place*.v
+pnr*.v
 abc.history
diff --git a/machxo2/examples/README.md b/machxo2/examples/README.md
index 87f50f6d..aac80fb4 100644
--- a/machxo2/examples/README.md
+++ b/machxo2/examples/README.md
@@ -2,18 +2,37 @@
 
 This contains a simple example of running `nextpnr-machxo2`:
 
-* `simple.sh` generates JSON output (`pnrblinky.json`) of a classic blinky
-  example from `blinky.v`.
+* `simple.sh` generates JSON output (`{pack,place,pnr}blinky.json`) of a
+  classic blinky example from `blinky.v`.
 * `simtest.sh` will use `yosys` to generate a Verilog file from
-  `pnrblinky.json`, called `pnrblinky.v`. It will then and compare
-  `pnrblinky.v`'s simulation behavior to the original verilog file (`blinky.v`)
-  using the [`iverilog`](http://iverilog.icarus.com) compiler and `vvp`
-  runtime. This is known as post-place-and-route simulation.
+  `{pack,place,pnr}blinky.json`, called `{pack,place,pnr}blinky.v`. It will
+  then and compare `{pack,place,pnr}blinky.v`'s simulation behavior to the
+  original verilog file (`blinky.v`) using the [`iverilog`](http://iverilog.icarus.com)
+  compiler and `vvp` runtime. This is known as post-place-and-route simulation.
+* `mitertest.sh` is similar to `simtest.sh`, but more comprehensive. This
+  script creates a [miter circuit](https://www21.in.tum.de/~lammich/2015_SS_Seminar_SAT/resources/Equivalence_Checking_11_30_08.pdf)
+  to compare the output port values of `{pack,place,pnr}blinky.v` against the
+  original `blinky.v` _when both modules are fed the same values on their input
+  ports._
 
-As `nextpnr-machxo2` is developed the contents `simple.sh` and `simtest.sh`
-are subject to change.
+  All possible inputs and resulting outputs can be tested in reasonable time by
+  using yosys' built-in SAT solver.
 
-## Environment Variables For `simple.sh` And `simtest.sh`
+As `nextpnr-machxo2` is developed the contents `simple.sh`, `simtest.sh`, and
+`mitertest.sh` are subject to change.
+
+## How To Run
+
+Each `sh` script runs yosys and nextpnr to validate a blinky design in various
+ways. The `mode` argument to each script- `pack`, `place`, or `pnr`- stop
+`nextpnr-machxo2` after the specified phase and writes out a JSON file of the
+results in `{pack,place,pnr}blinky.json`; `pnr` runs all of the Pack, Place,
+and Route phases.
+
+To keep file count lower, all yosys scripts are written inline inside the
+`sh` scripts using the `-p` option.
+
+## Environment Variables For Scripts
 
 * `YOSYS`- Set to the location of the `yosys` binary to test. Defaults to the
   `yosys` on the path. You may want to set this to a `yosys` binary in your
diff --git a/machxo2/examples/blinky.v b/machxo2/examples/blinky.v
index 2137ad58..57bad543 100644
--- a/machxo2/examples/blinky.v
+++ b/machxo2/examples/blinky.v
@@ -1,6 +1,10 @@
 module top(input clk, rst, output [7:0] leds);
 
-// TODO: Test miter circuit without reset value.
+// TODO: Test miter circuit without reset value. SAT and SMT diverge without
+// reset value (SAT succeeds, SMT fails). I haven't figured out the correct
+// init set of options to make SAT fail.
+// "sat -verify -prove-asserts -set-init-def -seq 1 miter" causes assertion
+// failure in yosys.
 reg [7:0] ctr = 8'h00;
 always @(posedge clk)
 	if (rst)
diff --git a/machxo2/examples/mitertest.sh b/machxo2/examples/mitertest.sh
new file mode 100644
index 00000000..e5cc5173
--- /dev/null
+++ b/machxo2/examples/mitertest.sh
@@ -0,0 +1,43 @@
+#!/usr/bin/env bash
+
+if [ $# -lt 1 ]; then
+    echo "Usage: $0 mode"
+    exit -1
+fi
+
+case $1 in
+    "pack")
+        NEXTPNR_MODE="--pack-only"
+        ;;
+    "place")
+        NEXTPNR_MODE="--no-route"
+        ;;
+    "pnr")
+        NEXTPNR_MODE=""
+        ;;
+    *)
+        echo "Mode string must be \"pack\", \"place\", or \"pnr\""
+        exit -2
+        ;;
+esac
+
+set -ex
+
+${YOSYS:-yosys} -p "read_verilog blinky.v
+                    synth_machxo2 -noiopad -json blinky.json
+                    show -format png -prefix blinky"
+${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --no-iobs --json blinky.json --write ${1}blinky.json
+${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
+                    read_json ${1}blinky.json
+                    clean -purge
+                    show -format png -prefix ${1}blinky
+                    write_verilog -noattr -norename ${1}blinky.v"
+${YOSYS:-yosys} -p "read_verilog blinky.v
+                    rename top gold
+                    read_verilog ${1}blinky.v
+                    rename top gate
+                    read_verilog +/machxo2/cells_sim.v
+
+                    miter -equiv -make_assert -flatten gold gate miter
+                    hierarchy -top miter
+                    sat -verify -prove-asserts -tempinduct miter"
diff --git a/machxo2/examples/simple.sh b/machxo2/examples/simple.sh
index 9eb06886..91fa4b91 100644
--- a/machxo2/examples/simple.sh
+++ b/machxo2/examples/simple.sh
@@ -1,5 +1,34 @@
 #!/usr/bin/env bash
+
+if [ $# -lt 1 ]; then
+    echo "Usage: $0 mode"
+    exit -1
+fi
+
+case $1 in
+    "pack")
+        NEXTPNR_MODE="--pack-only"
+        ;;
+    "place")
+        NEXTPNR_MODE="--no-route"
+        ;;
+    "pnr")
+        NEXTPNR_MODE=""
+        ;;
+    *)
+        echo "Mode string must be \"pack\", \"place\", or \"pnr\""
+        exit -2
+        ;;
+esac
+
 set -ex
-${YOSYS:yosys} -p "synth_machxo2 -json blinky.json" blinky.v
-${NEXTPNR:-../../nextpnr-machxo2} --json blinky.json --write pnrblinky.json
-${YOSYS:yosys} -p "read_verilog -lib +/machxo2/cells_sim.v; read_json pnrblinky.json; dump -o blinky.il; show -format png -prefix blinky"
+
+${YOSYS:-yosys} -p "read_verilog blinky.v
+                    synth_machxo2 -json blinky.json
+                    show -format png -prefix blinky"
+${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --no-iobs --json blinky.json --write ${1}blinky.json
+${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
+                    read_json ${1}blinky.json
+                    clean -purge
+                    show -format png -prefix ${1}blinky
+                    write_verilog -noattr -norename ${1}blinky.v"
diff --git a/machxo2/examples/simtest.sh b/machxo2/examples/simtest.sh
index 4cb8d5ca..ff35bbd6 100644
--- a/machxo2/examples/simtest.sh
+++ b/machxo2/examples/simtest.sh
@@ -1,7 +1,36 @@
 #!/usr/bin/env bash
+
+if [ $# -lt 1 ]; then
+    echo "Usage: $0 mode"
+    exit -1
+fi
+
+case $1 in
+    "pack")
+        NEXTPNR_MODE="--pack-only"
+        ;;
+    "place")
+        NEXTPNR_MODE="--no-route"
+        ;;
+    "pnr")
+        NEXTPNR_MODE=""
+        ;;
+    *)
+        echo "Mode string must be \"pack\", \"place\", or \"pnr\""
+        exit -2
+        ;;
+esac
+
 set -ex
-${YOSYS:-yosys} -p "synth_machxo2 -json blinky.json" blinky.v
-${NEXTPNR:-../../nextpnr-machxo2} --no-iobs --json blinky.json --write pnrblinky.json
-${YOSYS:-yosys} -p "read_json blinky.json; write_verilog  -noattr -norename pnrblinky.v"
-iverilog -o blinky_simtest ${CELLS_SIM:-`${YOSYS:yosys}-config --datdir/machxo2/cells_sim.v`} blinky_tb.v pnrblinky.v
+
+${YOSYS:-yosys} -p "read_verilog blinky.v
+                    synth_machxo2 -json blinky.json
+                    show -format png -prefix blinky"
+${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --no-iobs --json blinky.json --write ${1}blinky.json
+${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
+                    read_json ${1}blinky.json
+                    clean -purge
+                    show -format png -prefix ${1}blinky
+                    write_verilog -noattr -norename ${1}blinky.v"
+iverilog -o blinky_simtest ${CELLS_SIM:-`${YOSYS:yosys}-config --datdir/machxo2/cells_sim.v`} blinky_tb.v ${1}blinky.v
 vvp -N ./blinky_simtest
-- 
cgit v1.2.3


From 6ce2edc2f109f81adfb143d2732dabe6fc4e36de Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Sat, 28 Nov 2020 21:43:03 -0500
Subject: machxo2: Add SMT mode to mitertest.sh

---
 machxo2/examples/.gitignore   |  2 ++
 machxo2/examples/README.md    |  9 ++++++-
 machxo2/examples/mitertest.sh | 61 +++++++++++++++++++++++++++++++++++--------
 3 files changed, 60 insertions(+), 12 deletions(-)

(limited to 'machxo2/examples')

diff --git a/machxo2/examples/.gitignore b/machxo2/examples/.gitignore
index a4c8185f..87d5128b 100644
--- a/machxo2/examples/.gitignore
+++ b/machxo2/examples/.gitignore
@@ -1,6 +1,8 @@
 /blinky_simtest
 *.vcd
 *.png
+*.log
+*.smt2
 pack*.v
 place*.v
 pnr*.v
diff --git a/machxo2/examples/README.md b/machxo2/examples/README.md
index aac80fb4..e940c01c 100644
--- a/machxo2/examples/README.md
+++ b/machxo2/examples/README.md
@@ -16,7 +16,8 @@ This contains a simple example of running `nextpnr-machxo2`:
   ports._
 
   All possible inputs and resulting outputs can be tested in reasonable time by
-  using yosys' built-in SAT solver.
+  using `yosys`' built-in SAT solver or [`z3`](https://github.com/Z3Prover/z3),
+  an external SMT solver.
 
 As `nextpnr-machxo2` is developed the contents `simple.sh`, `simtest.sh`, and
 `mitertest.sh` are subject to change.
@@ -29,9 +30,15 @@ ways. The `mode` argument to each script- `pack`, `place`, or `pnr`- stop
 results in `{pack,place,pnr}blinky.json`; `pnr` runs all of the Pack, Place,
 and Route phases.
 
+`mitertest.sh` requires an additional option- `sat` or `smt`- to choose between
+verifying the miter with either yosys' built-in SAT solver, or an external
+SMT solver.
+
 To keep file count lower, all yosys scripts are written inline inside the
 `sh` scripts using the `-p` option.
 
+To clean output files, run: `rm -rf *.dot *.json *.png *.vcd *.smt2 *.log {pack,place,pnr}*.v blinky_simtest*`
+
 ## Environment Variables For Scripts
 
 * `YOSYS`- Set to the location of the `yosys` binary to test. Defaults to the
diff --git a/machxo2/examples/mitertest.sh b/machxo2/examples/mitertest.sh
index e5cc5173..aea5bfff 100644
--- a/machxo2/examples/mitertest.sh
+++ b/machxo2/examples/mitertest.sh
@@ -1,7 +1,7 @@
 #!/usr/bin/env bash
 
 if [ $# -lt 1 ]; then
-    echo "Usage: $0 mode"
+    echo "Usage: $0 nextpnr_mode solve_mode"
     exit -1
 fi
 
@@ -16,11 +16,53 @@ case $1 in
         NEXTPNR_MODE=""
         ;;
     *)
-        echo "Mode string must be \"pack\", \"place\", or \"pnr\""
+        echo "nextpnr_mode string must be \"pack\", \"place\", or \"pnr\""
         exit -2
         ;;
 esac
 
+case $2 in
+    "sat")
+        SAT=1
+        ;;
+    "smt")
+        SMT=1
+        ;;
+    *)
+        echo "solve_mode string must be \"sat\", or \"smt\""
+        exit -3
+        ;;
+esac
+
+do_sat() {
+    ${YOSYS:-yosys} -l ${1}miter_sat.log -p "read_verilog blinky.v
+                        rename top gold
+                        read_verilog ${1}blinky.v
+                        rename top gate
+                        read_verilog +/machxo2/cells_sim.v
+
+                        miter -equiv -make_assert -flatten gold gate ${1}miter
+                        hierarchy -top ${1}miter
+                        sat -verify -prove-asserts -tempinduct ${1}miter"
+}
+
+do_smt() {
+    ${YOSYS:-yosys} -l ${1}miter_smt.log -p "read_verilog blinky.v
+                        rename top gold
+                        read_verilog ${1}blinky.v
+                        rename top gate
+                        read_verilog +/machxo2/cells_sim.v
+
+                        miter -equiv -make_assert gold gate ${1}miter
+                        hierarchy -auto-top -check; proc;
+                        opt_clean
+                        write_verilog ${1}miter.v
+                        write_smt2 ${1}miter.smt2"
+
+    yosys-smtbmc -s z3 --dump-vcd ${1}miter_bmc.vcd ${1}miter.smt2
+    yosys-smtbmc -s z3 -i --dump-vcd ${1}miter_tmp.vcd ${1}miter.smt2
+}
+
 set -ex
 
 ${YOSYS:-yosys} -p "read_verilog blinky.v
@@ -32,12 +74,9 @@ ${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
                     clean -purge
                     show -format png -prefix ${1}blinky
                     write_verilog -noattr -norename ${1}blinky.v"
-${YOSYS:-yosys} -p "read_verilog blinky.v
-                    rename top gold
-                    read_verilog ${1}blinky.v
-                    rename top gate
-                    read_verilog +/machxo2/cells_sim.v
-
-                    miter -equiv -make_assert -flatten gold gate miter
-                    hierarchy -top miter
-                    sat -verify -prove-asserts -tempinduct miter"
+
+if [ $2 = "sat" ]; then
+    do_sat $1
+elif [ $2 = "smt" ]; then
+    do_smt $1
+fi
-- 
cgit v1.2.3


From ec4a9685abf0fd7d7b2cfecc5dbfc09b963b6ea8 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Sat, 5 Dec 2020 00:38:00 -0500
Subject: machxo2: Initialize Arch context with device type and package.

---
 machxo2/examples/mitertest.sh | 2 +-
 machxo2/examples/simple.sh    | 2 +-
 machxo2/examples/simtest.sh   | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'machxo2/examples')

diff --git a/machxo2/examples/mitertest.sh b/machxo2/examples/mitertest.sh
index aea5bfff..5190af31 100644
--- a/machxo2/examples/mitertest.sh
+++ b/machxo2/examples/mitertest.sh
@@ -68,7 +68,7 @@ set -ex
 ${YOSYS:-yosys} -p "read_verilog blinky.v
                     synth_machxo2 -noiopad -json blinky.json
                     show -format png -prefix blinky"
-${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --no-iobs --json blinky.json --write ${1}blinky.json
+${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --no-iobs --json blinky.json --write ${1}blinky.json
 ${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
                     read_json ${1}blinky.json
                     clean -purge
diff --git a/machxo2/examples/simple.sh b/machxo2/examples/simple.sh
index 91fa4b91..c977bf1a 100644
--- a/machxo2/examples/simple.sh
+++ b/machxo2/examples/simple.sh
@@ -26,7 +26,7 @@ set -ex
 ${YOSYS:-yosys} -p "read_verilog blinky.v
                     synth_machxo2 -json blinky.json
                     show -format png -prefix blinky"
-${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --no-iobs --json blinky.json --write ${1}blinky.json
+${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --no-iobs --json blinky.json --write ${1}blinky.json
 ${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
                     read_json ${1}blinky.json
                     clean -purge
diff --git a/machxo2/examples/simtest.sh b/machxo2/examples/simtest.sh
index ff35bbd6..53f2e728 100644
--- a/machxo2/examples/simtest.sh
+++ b/machxo2/examples/simtest.sh
@@ -26,7 +26,7 @@ set -ex
 ${YOSYS:-yosys} -p "read_verilog blinky.v
                     synth_machxo2 -json blinky.json
                     show -format png -prefix blinky"
-${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --no-iobs --json blinky.json --write ${1}blinky.json
+${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --no-iobs --json blinky.json --write ${1}blinky.json
 ${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
                     read_json ${1}blinky.json
                     clean -purge
-- 
cgit v1.2.3


From d0b822c0365c52a8a8439094f2268cfa0c461b5e Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Sun, 31 Jan 2021 22:42:15 -0500
Subject: machxo2: Add demo.sh TinyFPGA Ax example.

---
 machxo2/examples/.gitignore |  2 ++
 machxo2/examples/README.md  | 11 ++++++++++-
 machxo2/examples/demo.sh    | 10 ++++++++++
 machxo2/examples/tinyfpga.v | 28 ++++++++++++++++++++++++++++
 4 files changed, 50 insertions(+), 1 deletion(-)
 create mode 100644 machxo2/examples/demo.sh
 create mode 100644 machxo2/examples/tinyfpga.v

(limited to 'machxo2/examples')

diff --git a/machxo2/examples/.gitignore b/machxo2/examples/.gitignore
index 87d5128b..91167252 100644
--- a/machxo2/examples/.gitignore
+++ b/machxo2/examples/.gitignore
@@ -7,3 +7,5 @@ pack*.v
 place*.v
 pnr*.v
 abc.history
+/tinyfpga.txt
+/tinyfpga.bit
diff --git a/machxo2/examples/README.md b/machxo2/examples/README.md
index e940c01c..bcffeea3 100644
--- a/machxo2/examples/README.md
+++ b/machxo2/examples/README.md
@@ -18,11 +18,16 @@ This contains a simple example of running `nextpnr-machxo2`:
   All possible inputs and resulting outputs can be tested in reasonable time by
   using `yosys`' built-in SAT solver or [`z3`](https://github.com/Z3Prover/z3),
   an external SMT solver.
+* `demo.sh` creates a blinky bitstream for [TinyFPGA Ax](https://tinyfpga.com/a-series-guide.html)
+  and writes the resulting bitstream to MachXO2's internal flash using
+  [`tinyproga`](https://github.com/tinyfpga/TinyFPGA-A-Programmer).
 
 As `nextpnr-machxo2` is developed the contents `simple.sh`, `simtest.sh`, and
 `mitertest.sh` are subject to change.
 
 ## How To Run
+The following applies to all `sh` scripts except `demo.sh`, which requires no
+arguments.
 
 Each `sh` script runs yosys and nextpnr to validate a blinky design in various
 ways. The `mode` argument to each script- `pack`, `place`, or `pnr`- stop
@@ -37,7 +42,8 @@ SMT solver.
 To keep file count lower, all yosys scripts are written inline inside the
 `sh` scripts using the `-p` option.
 
-To clean output files, run: `rm -rf *.dot *.json *.png *.vcd *.smt2 *.log {pack,place,pnr}*.v blinky_simtest*`
+### Clean
+To clean output files from _all_ scripts, run: `rm -rf *.dot *.json *.png *.vcd *.smt2 *.log tinyfpga.txt tinyfpga.bit {pack,place,pnr}*.v blinky_simtest*`
 
 ## Environment Variables For Scripts
 
@@ -53,3 +59,6 @@ To clean output files, run: `rm -rf *.dot *.json *.png *.vcd *.smt2 *.log {pack,
   returns. You may want to set this to `/path/to/yosys/src/share/machxo2/cells_sim.v`
   if doing development; `yosys-config` cannot find these "before-installation"
   simulation models.
+* `TRELLIS_DB`- Set to the location of the Project Trellis database to use.
+  Defaults to nothing, which means `ecppack` will use whatever database is on
+  its path.
diff --git a/machxo2/examples/demo.sh b/machxo2/examples/demo.sh
new file mode 100644
index 00000000..6979f111
--- /dev/null
+++ b/machxo2/examples/demo.sh
@@ -0,0 +1,10 @@
+#!/bin/sh
+
+if [ ! -z ${TRELLIS_DB+x} ]; then
+    DB_ARG="--db $TRELLIS_DB"
+fi
+
+${YOSYS:-yosys} -p 'synth_machxo2 -json tinyfpga.json' tinyfpga.v
+${NEXTPNR:-../../nextpnr-machxo2} --1200 --package QFN32 --no-iobs --json tinyfpga.json --textcfg tinyfpga.txt
+ecppack --compress $DB_ARG tinyfpga.txt tinyfpga.bit
+tinyproga -b tinyfpga.bit
diff --git a/machxo2/examples/tinyfpga.v b/machxo2/examples/tinyfpga.v
new file mode 100644
index 00000000..dfc2710d
--- /dev/null
+++ b/machxo2/examples/tinyfpga.v
@@ -0,0 +1,28 @@
+// Modified from:
+// https://github.com/tinyfpga/TinyFPGA-A-Series/tree/master/template_a2
+// https://tinyfpga.com/a-series-guide.html used as a basis.
+
+module TinyFPGA_A2 (
+  (* LOC="13" *)
+  inout pin1
+);
+
+
+  wire clk;
+
+  OSCH #(
+    .NOM_FREQ("16.63")
+  ) internal_oscillator_inst (
+    .STDBY(1'b0),
+    .OSC(clk)
+  );
+
+  reg [23:0] led_timer;
+
+  always @(posedge clk) begin
+    led_timer <= led_timer + 1;
+  end
+
+  // left side of board
+  assign pin1 = led_timer[23];
+endmodule
-- 
cgit v1.2.3


From b9eb443e549ab8c81e0c6bc94538f9f2fe2821d4 Mon Sep 17 00:00:00 2001
From: mtnrbq <rmawston@live.com.au>
Date: Thu, 4 Feb 2021 07:31:14 +1100
Subject: Add demo with RGB LED

---
 machxo2/examples/demorgb.sh | 10 ++++++++++
 machxo2/examples/rgbcount.v | 33 +++++++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+)
 create mode 100644 machxo2/examples/demorgb.sh
 create mode 100644 machxo2/examples/rgbcount.v

(limited to 'machxo2/examples')

diff --git a/machxo2/examples/demorgb.sh b/machxo2/examples/demorgb.sh
new file mode 100644
index 00000000..f68db8c3
--- /dev/null
+++ b/machxo2/examples/demorgb.sh
@@ -0,0 +1,10 @@
+#!/bin/sh
+
+if [ ! -z ${TRELLIS_DB+x} ]; then
+    DB_ARG="--db $TRELLIS_DB"
+fi
+
+${YOSYS:-yosys} -p 'synth_machxo2 -json rgbcount.json' rgbcount.v
+${NEXTPNR:-../../nextpnr-machxo2} --1200 --package QFN32 --no-iobs --json rgbcount.json --textcfg rgbcount.txt
+ecppack --compress $DB_ARG rgbcount.txt rgbcount.bit
+tinyproga -b rgbcount.bit
diff --git a/machxo2/examples/rgbcount.v b/machxo2/examples/rgbcount.v
new file mode 100644
index 00000000..230fc73c
--- /dev/null
+++ b/machxo2/examples/rgbcount.v
@@ -0,0 +1,33 @@
+// Modified from:
+// https://github.com/tinyfpga/TinyFPGA-A-Series/tree/master/template_a2
+// https://tinyfpga.com/a-series-guide.html used as a basis.
+
+module TinyFPGA_A2 (
+  (* LOC="21" *)
+  inout pin6,
+  (* LOC="26" *)
+  inout pin9_jtgnb,
+  (* LOC="27" *)
+  inout pin10_sda,
+);
+  wire clk;
+  
+  OSCH #(
+    .NOM_FREQ("2.08")
+  ) internal_oscillator_inst (
+    .STDBY(1'b0), 
+    .OSC(clk)
+  ); 
+  
+  reg [23:0] led_timer;
+  
+  always @(posedge clk) begin
+    led_timer <= led_timer + 1; 
+  end
+  
+  // left side of board
+  assign pin9_jtgnb = led_timer[23];
+  assign pin10_sda = led_timer[22];
+  assign pin6 = led_timer[21];
+
+endmodule
\ No newline at end of file
-- 
cgit v1.2.3


From 0aa472fb3adac0b76ef0b69831d5b83ff1200fe2 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Mon, 8 Feb 2021 00:07:39 -0500
Subject: machxo2: Add prefix paramter to demo.sh.

---
 machxo2/examples/.gitignore |  4 ++--
 machxo2/examples/README.md  | 25 +++++++++++++++++++------
 machxo2/examples/demo.sh    | 20 ++++++++++++++++----
 machxo2/examples/demorgb.sh | 10 ----------
 4 files changed, 37 insertions(+), 22 deletions(-)
 delete mode 100644 machxo2/examples/demorgb.sh

(limited to 'machxo2/examples')

diff --git a/machxo2/examples/.gitignore b/machxo2/examples/.gitignore
index 91167252..955c6e29 100644
--- a/machxo2/examples/.gitignore
+++ b/machxo2/examples/.gitignore
@@ -7,5 +7,5 @@ pack*.v
 place*.v
 pnr*.v
 abc.history
-/tinyfpga.txt
-/tinyfpga.bit
+*.txt
+*.bit
diff --git a/machxo2/examples/README.md b/machxo2/examples/README.md
index bcffeea3..fd84dc93 100644
--- a/machxo2/examples/README.md
+++ b/machxo2/examples/README.md
@@ -18,16 +18,14 @@ This contains a simple example of running `nextpnr-machxo2`:
   All possible inputs and resulting outputs can be tested in reasonable time by
   using `yosys`' built-in SAT solver or [`z3`](https://github.com/Z3Prover/z3),
   an external SMT solver.
-* `demo.sh` creates a blinky bitstream for [TinyFPGA Ax](https://tinyfpga.com/a-series-guide.html)
+* `demo.sh` creates bitstreams for [TinyFPGA Ax](https://tinyfpga.com/a-series-guide.html)
   and writes the resulting bitstream to MachXO2's internal flash using
   [`tinyproga`](https://github.com/tinyfpga/TinyFPGA-A-Programmer).
 
-As `nextpnr-machxo2` is developed the contents `simple.sh`, `simtest.sh`, and
-`mitertest.sh` are subject to change.
+As `nextpnr-machxo2` is developed the contents `simple.sh`, `simtest.sh`, `mitertest.sh`, and `demo.sh` are subject to change.
 
 ## How To Run
-The following applies to all `sh` scripts except `demo.sh`, which requires no
-arguments.
+The following applies to all `sh` scripts except `demo.sh`.
 
 Each `sh` script runs yosys and nextpnr to validate a blinky design in various
 ways. The `mode` argument to each script- `pack`, `place`, or `pnr`- stop
@@ -42,8 +40,23 @@ SMT solver.
 To keep file count lower, all yosys scripts are written inline inside the
 `sh` scripts using the `-p` option.
 
+`demo.sh` requires a prefix that matches one of the self-contained Verilog
+examples in this directory. For instance, to create a bitstream from
+`tinyfpga.v`, use `demo.sh tinyfpga`. The script will catch Verilog files which
+are not meant to be programmed onto TinyFPA Ax.
+
 ### Clean
-To clean output files from _all_ scripts, run: `rm -rf *.dot *.json *.png *.vcd *.smt2 *.log tinyfpga.txt tinyfpga.bit {pack,place,pnr}*.v blinky_simtest*`
+To clean output files from _all_ scripts, run:
+
+```
+rm -rf *.dot *.json *.png *.vcd *.smt2 *.log *.txt *.bit {pack,place,pnr}*.v blinky_simtest*
+```
+
+## Verilog Examples
+* `blinky.v`/`blinky_tb.v`- A blinky example meant for simulation.
+* `tinyfpga.v`- Blink the LED on TinyFPA Ax.
+* `rgbcount.v`- Blink an RGB LED using TinyFPGA Ax, more closely-based on
+  [the TinyFPGA Ax guide](https://tinyfpga.com/a-series-guide.html).
 
 ## Environment Variables For Scripts
 
diff --git a/machxo2/examples/demo.sh b/machxo2/examples/demo.sh
index 6979f111..00cb0cd0 100644
--- a/machxo2/examples/demo.sh
+++ b/machxo2/examples/demo.sh
@@ -1,10 +1,22 @@
 #!/bin/sh
 
+if [ $# -lt 1 ]; then
+    echo "Usage: $0 prefix"
+    exit -1
+fi
+
+if ! grep -q "(\*.*LOC.*\*)" $1.v; then
+    echo "$1.v does not have LOC constraints for tinyfpga_a."
+    exit -2
+fi
+
 if [ ! -z ${TRELLIS_DB+x} ]; then
     DB_ARG="--db $TRELLIS_DB"
 fi
 
-${YOSYS:-yosys} -p 'synth_machxo2 -json tinyfpga.json' tinyfpga.v
-${NEXTPNR:-../../nextpnr-machxo2} --1200 --package QFN32 --no-iobs --json tinyfpga.json --textcfg tinyfpga.txt
-ecppack --compress $DB_ARG tinyfpga.txt tinyfpga.bit
-tinyproga -b tinyfpga.bit
+set -ex
+
+${YOSYS:-yosys} -p "synth_machxo2 -json $1.json" $1.v
+${NEXTPNR:-../../nextpnr-machxo2} --1200 --package QFN32 --no-iobs --json $1.json --textcfg $1.txt
+ecppack --compress $DB_ARG $1.txt $1.bit
+tinyproga -b $1.bit
diff --git a/machxo2/examples/demorgb.sh b/machxo2/examples/demorgb.sh
deleted file mode 100644
index f68db8c3..00000000
--- a/machxo2/examples/demorgb.sh
+++ /dev/null
@@ -1,10 +0,0 @@
-#!/bin/sh
-
-if [ ! -z ${TRELLIS_DB+x} ]; then
-    DB_ARG="--db $TRELLIS_DB"
-fi
-
-${YOSYS:-yosys} -p 'synth_machxo2 -json rgbcount.json' rgbcount.v
-${NEXTPNR:-../../nextpnr-machxo2} --1200 --package QFN32 --no-iobs --json rgbcount.json --textcfg rgbcount.txt
-ecppack --compress $DB_ARG rgbcount.txt rgbcount.bit
-tinyproga -b rgbcount.bit
-- 
cgit v1.2.3


From a3a38b0536a59be8f2fd7afd1914989d0ed23da7 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Mon, 8 Feb 2021 01:37:14 -0500
Subject: machxo2: Add prefix parameter to mitertest.sh. All Verilog files top
 modules named "top".

---
 machxo2/examples/mitertest.sh | 54 +++++++++++++++++++++----------------------
 machxo2/examples/rgbcount.v   | 18 +++++++--------
 machxo2/examples/tinyfpga.v   |  2 +-
 3 files changed, 37 insertions(+), 37 deletions(-)

(limited to 'machxo2/examples')

diff --git a/machxo2/examples/mitertest.sh b/machxo2/examples/mitertest.sh
index 5190af31..f2c7ba57 100644
--- a/machxo2/examples/mitertest.sh
+++ b/machxo2/examples/mitertest.sh
@@ -1,11 +1,11 @@
 #!/usr/bin/env bash
 
-if [ $# -lt 1 ]; then
-    echo "Usage: $0 nextpnr_mode solve_mode"
+if [ $# -lt 3 ]; then
+    echo "Usage: $0 prefix nextpnr_mode solve_mode"
     exit -1
 fi
 
-case $1 in
+case $2 in
     "pack")
         NEXTPNR_MODE="--pack-only"
         ;;
@@ -21,7 +21,7 @@ case $1 in
         ;;
 esac
 
-case $2 in
+case $3 in
     "sat")
         SAT=1
         ;;
@@ -35,48 +35,48 @@ case $2 in
 esac
 
 do_sat() {
-    ${YOSYS:-yosys} -l ${1}miter_sat.log -p "read_verilog blinky.v
+    ${YOSYS:-yosys} -l ${2}${1}_miter_sat.log -p "read_verilog ${1}.v
                         rename top gold
-                        read_verilog ${1}blinky.v
+                        read_verilog ${2}${1}.v
                         rename top gate
                         read_verilog +/machxo2/cells_sim.v
 
-                        miter -equiv -make_assert -flatten gold gate ${1}miter
-                        hierarchy -top ${1}miter
-                        sat -verify -prove-asserts -tempinduct ${1}miter"
+                        miter -equiv -make_assert -flatten gold gate ${2}${1}_miter
+                        hierarchy -top ${2}${1}_miter
+                        sat -verify -prove-asserts -tempinduct ${2}${1}_miter"
 }
 
 do_smt() {
-    ${YOSYS:-yosys} -l ${1}miter_smt.log -p "read_verilog blinky.v
+    ${YOSYS:-yosys} -l ${2}${1}_miter_smt.log -p "read_verilog ${1}.v
                         rename top gold
-                        read_verilog ${1}blinky.v
+                        read_verilog ${2}${1}.v
                         rename top gate
                         read_verilog +/machxo2/cells_sim.v
 
-                        miter -equiv -make_assert gold gate ${1}miter
+                        miter -equiv -make_assert gold gate ${2}${1}_miter
                         hierarchy -auto-top -check; proc;
                         opt_clean
-                        write_verilog ${1}miter.v
-                        write_smt2 ${1}miter.smt2"
+                        write_verilog ${2}${1}_miter.v
+                        write_smt2 ${2}${1}_miter.smt2"
 
-    yosys-smtbmc -s z3 --dump-vcd ${1}miter_bmc.vcd ${1}miter.smt2
-    yosys-smtbmc -s z3 -i --dump-vcd ${1}miter_tmp.vcd ${1}miter.smt2
+    yosys-smtbmc -s z3 --dump-vcd ${2}${1}_miter_bmc.vcd ${2}${1}_miter.smt2
+    yosys-smtbmc -s z3 -i --dump-vcd ${2}${1}_miter_tmp.vcd ${2}${1}_miter.smt2
 }
 
 set -ex
 
-${YOSYS:-yosys} -p "read_verilog blinky.v
-                    synth_machxo2 -noiopad -json blinky.json
-                    show -format png -prefix blinky"
-${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --no-iobs --json blinky.json --write ${1}blinky.json
+${YOSYS:-yosys} -p "read_verilog ${1}.v
+                    synth_machxo2 -noiopad -json ${1}.json"
+# FIXME: --json option really not needed here.
+${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --no-iobs --json ${1}.json --write ${2}${1}.json
 ${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
-                    read_json ${1}blinky.json
+                    read_json ${2}${1}.json
                     clean -purge
-                    show -format png -prefix ${1}blinky
-                    write_verilog -noattr -norename ${1}blinky.v"
+                    show -format png -prefix ${2}${1}
+                    write_verilog -noattr -norename ${2}${1}.v"
 
-if [ $2 = "sat" ]; then
-    do_sat $1
-elif [ $2 = "smt" ]; then
-    do_smt $1
+if [ $3 = "sat" ]; then
+    do_sat $1 $2
+elif [ $3 = "smt" ]; then
+    do_smt $1 $2
 fi
diff --git a/machxo2/examples/rgbcount.v b/machxo2/examples/rgbcount.v
index 230fc73c..bf5c7518 100644
--- a/machxo2/examples/rgbcount.v
+++ b/machxo2/examples/rgbcount.v
@@ -2,7 +2,7 @@
 // https://github.com/tinyfpga/TinyFPGA-A-Series/tree/master/template_a2
 // https://tinyfpga.com/a-series-guide.html used as a basis.
 
-module TinyFPGA_A2 (
+module top (
   (* LOC="21" *)
   inout pin6,
   (* LOC="26" *)
@@ -11,23 +11,23 @@ module TinyFPGA_A2 (
   inout pin10_sda,
 );
   wire clk;
-  
+
   OSCH #(
     .NOM_FREQ("2.08")
   ) internal_oscillator_inst (
-    .STDBY(1'b0), 
+    .STDBY(1'b0),
     .OSC(clk)
-  ); 
-  
+  );
+
   reg [23:0] led_timer;
-  
+
   always @(posedge clk) begin
-    led_timer <= led_timer + 1; 
+    led_timer <= led_timer + 1;
   end
-  
+
   // left side of board
   assign pin9_jtgnb = led_timer[23];
   assign pin10_sda = led_timer[22];
   assign pin6 = led_timer[21];
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/machxo2/examples/tinyfpga.v b/machxo2/examples/tinyfpga.v
index dfc2710d..bd26d8eb 100644
--- a/machxo2/examples/tinyfpga.v
+++ b/machxo2/examples/tinyfpga.v
@@ -2,7 +2,7 @@
 // https://github.com/tinyfpga/TinyFPGA-A-Series/tree/master/template_a2
 // https://tinyfpga.com/a-series-guide.html used as a basis.
 
-module TinyFPGA_A2 (
+module top (
   (* LOC="13" *)
   inout pin1
 );
-- 
cgit v1.2.3


From 2b54e87548befa65ce058d23aec82d389190ba55 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Mon, 8 Feb 2021 01:43:06 -0500
Subject: machxo2: Verilog examples using OSCH cannot be simulated in
 mitertest.sh. Remove show from mitertest.sh.

---
 machxo2/examples/mitertest.sh | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

(limited to 'machxo2/examples')

diff --git a/machxo2/examples/mitertest.sh b/machxo2/examples/mitertest.sh
index f2c7ba57..06b99125 100644
--- a/machxo2/examples/mitertest.sh
+++ b/machxo2/examples/mitertest.sh
@@ -5,6 +5,11 @@ if [ $# -lt 3 ]; then
     exit -1
 fi
 
+if grep -q "OSCH" $1.v; then
+    echo "$1.v uses blackbox primitive OSCH and cannot be simulated."
+    exit -2
+fi
+
 case $2 in
     "pack")
         NEXTPNR_MODE="--pack-only"
@@ -17,7 +22,7 @@ case $2 in
         ;;
     *)
         echo "nextpnr_mode string must be \"pack\", \"place\", or \"pnr\""
-        exit -2
+        exit -3
         ;;
 esac
 
@@ -30,7 +35,7 @@ case $3 in
         ;;
     *)
         echo "solve_mode string must be \"sat\", or \"smt\""
-        exit -3
+        exit -4
         ;;
 esac
 
@@ -72,7 +77,6 @@ ${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --no-iobs
 ${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
                     read_json ${2}${1}.json
                     clean -purge
-                    show -format png -prefix ${2}${1}
                     write_verilog -noattr -norename ${2}${1}.v"
 
 if [ $3 = "sat" ]; then
-- 
cgit v1.2.3


From 77bb3e73cd2cb771d04522f4b8e33017a28424c7 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Mon, 8 Feb 2021 01:45:42 -0500
Subject: machxo2: Fix unhelpful comment in mitertest.sh.

---
 machxo2/examples/mitertest.sh | 1 -
 1 file changed, 1 deletion(-)

(limited to 'machxo2/examples')

diff --git a/machxo2/examples/mitertest.sh b/machxo2/examples/mitertest.sh
index 06b99125..14c6fe61 100644
--- a/machxo2/examples/mitertest.sh
+++ b/machxo2/examples/mitertest.sh
@@ -72,7 +72,6 @@ set -ex
 
 ${YOSYS:-yosys} -p "read_verilog ${1}.v
                     synth_machxo2 -noiopad -json ${1}.json"
-# FIXME: --json option really not needed here.
 ${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --no-iobs --json ${1}.json --write ${2}${1}.json
 ${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
                     read_json ${2}${1}.json
-- 
cgit v1.2.3


From 74b5e846a526670dcef78da73c5bf95d61d82a90 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Mon, 8 Feb 2021 02:28:03 -0500
Subject: machxo2: auto-top does not work for smt miter either.

---
 machxo2/examples/mitertest.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'machxo2/examples')

diff --git a/machxo2/examples/mitertest.sh b/machxo2/examples/mitertest.sh
index 14c6fe61..cfae28b7 100644
--- a/machxo2/examples/mitertest.sh
+++ b/machxo2/examples/mitertest.sh
@@ -59,7 +59,7 @@ do_smt() {
                         read_verilog +/machxo2/cells_sim.v
 
                         miter -equiv -make_assert gold gate ${2}${1}_miter
-                        hierarchy -auto-top -check; proc;
+                        hierarchy -top ${2}${1}_miter; proc;
                         opt_clean
                         write_verilog ${2}${1}_miter.v
                         write_smt2 ${2}${1}_miter.smt2"
-- 
cgit v1.2.3


From 73c851d8e0073010329edc6c9e5de7d63037fefe Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Mon, 8 Feb 2021 03:27:49 -0500
Subject: machxo2: Add two new examples: blinky_ext and aforementioned UART.

---
 machxo2/examples/README.md    |  10 ++
 machxo2/examples/blinky_ext.v |  19 ++++
 machxo2/examples/uart.v       | 209 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 238 insertions(+)
 create mode 100644 machxo2/examples/blinky_ext.v
 create mode 100644 machxo2/examples/uart.v

(limited to 'machxo2/examples')

diff --git a/machxo2/examples/README.md b/machxo2/examples/README.md
index fd84dc93..977d6d8a 100644
--- a/machxo2/examples/README.md
+++ b/machxo2/examples/README.md
@@ -57,6 +57,16 @@ rm -rf *.dot *.json *.png *.vcd *.smt2 *.log *.txt *.bit {pack,place,pnr}*.v bli
 * `tinyfpga.v`- Blink the LED on TinyFPA Ax.
 * `rgbcount.v`- Blink an RGB LED using TinyFPGA Ax, more closely-based on
   [the TinyFPGA Ax guide](https://tinyfpga.com/a-series-guide.html).
+* `blinky_ext.v`- Blink the LED on TinyFPA Ax using an external pin (pin 6).
+* `uart.v`- UART loopback demo at 19200 baud. Requires the following pins:
+  * Pin 1- RX LED
+  * Pin 2- TX (will echo RX)
+  * Pin 3- RX
+  * Pin 4- TX LED
+  * Pin 5- Load LED
+  * Pin 6- 12 MHz clock input
+  * Pin 7- Take LED
+  * Pin 8- Empty LED
 
 ## Environment Variables For Scripts
 
diff --git a/machxo2/examples/blinky_ext.v b/machxo2/examples/blinky_ext.v
new file mode 100644
index 00000000..a8bdd588
--- /dev/null
+++ b/machxo2/examples/blinky_ext.v
@@ -0,0 +1,19 @@
+// Modified from:
+// https://github.com/tinyfpga/TinyFPGA-A-Series/tree/master/template_a2
+
+module top (
+  (* LOC="13" *)
+  output pin1,
+  (* LOC="21" *)
+  input clk
+);
+
+  reg [23:0] led_timer;
+
+  always @(posedge clk) begin
+    led_timer <= led_timer + 1;
+  end
+
+  // left side of board
+  assign pin1 = led_timer[23];
+endmodule
diff --git a/machxo2/examples/uart.v b/machxo2/examples/uart.v
new file mode 100644
index 00000000..f1d95bd8
--- /dev/null
+++ b/machxo2/examples/uart.v
@@ -0,0 +1,209 @@
+/* Example UART derived from: https://github.com/cr1901/migen_uart.
+   Requires 12MHz clock and runs at 19,200 baud. */
+
+/* Machine-generated using Migen */
+
+module top(
+	(* LOC = "14" *)
+	output tx,
+	(* LOC = "16" *)
+	input rx,
+	(* LOC = "13" *)
+	output rx_led,
+	(* LOC = "17" *)
+	output tx_led,
+	(* LOC = "20" *)
+	output load_led,
+	(* LOC = "23" *)
+	output take_led,
+	(* LOC = "25" *)
+	output empty_led,
+	(* LOC = "21" *)
+	input clk
+);
+
+wire [7:0] out_data;
+wire [7:0] in_data;
+reg wr = 1'd0;
+reg rd = 1'd0;
+wire tx_empty;
+wire rx_empty;
+wire tx_ov;
+wire rx_ov;
+wire sout_load;
+wire [7:0] sout_out_data;
+wire sout_shift;
+reg sout_empty = 1'd1;
+reg sout_overrun = 1'd0;
+reg [3:0] sout_count = 4'd0;
+reg [9:0] sout_reg = 10'd0;
+reg sout_tx;
+wire sin_rx;
+wire sin_shift;
+wire sin_take;
+reg [7:0] sin_in_data = 8'd0;
+wire sin_edge;
+reg sin_empty = 1'd1;
+reg sin_busy = 1'd0;
+reg sin_overrun = 1'd0;
+reg sin_sync_rx = 1'd0;
+reg [8:0] sin_reg = 9'd0;
+reg sin_rx_prev = 1'd0;
+reg [3:0] sin_count = 4'd0;
+wire out_active;
+wire in_active;
+reg shift_out_strobe = 1'd0;
+reg shift_in_strobe = 1'd0;
+reg [9:0] in_counter = 10'd0;
+reg [9:0] out_counter = 10'd0;
+wire sys_clk;
+wire sys_rst;
+wire por_clk;
+reg int_rst = 1'd1;
+
+// synthesis translate_off
+reg dummy_s;
+initial dummy_s <= 1'd0;
+// synthesis translate_on
+
+assign tx_led = (~tx);
+assign rx_led = (~rx);
+assign load_led = sout_load;
+assign take_led = sin_take;
+assign empty_led = sin_empty;
+assign out_data = in_data;
+assign in_data = sin_in_data;
+assign sout_out_data = out_data;
+assign sin_take = rd;
+assign sout_load = wr;
+assign tx = sout_tx;
+assign sin_rx = rx;
+assign tx_empty = sout_empty;
+assign rx_empty = sin_empty;
+assign tx_ov = sout_overrun;
+assign rx_ov = sin_overrun;
+assign sout_shift = shift_out_strobe;
+assign sin_shift = shift_in_strobe;
+assign out_active = (~sout_empty);
+assign in_active = sin_busy;
+
+// synthesis translate_off
+reg dummy_d;
+// synthesis translate_on
+always @(*) begin
+	sout_tx <= 1'd0;
+	if (sout_empty) begin
+		sout_tx <= 1'd1;
+	end else begin
+		sout_tx <= sout_reg[0];
+	end
+// synthesis translate_off
+	dummy_d <= dummy_s;
+// synthesis translate_on
+end
+assign sin_edge = ((sin_rx_prev == 1'd1) & (sin_sync_rx == 1'd0));
+assign sys_clk = clk;
+assign por_clk = clk;
+assign sys_rst = int_rst;
+
+always @(posedge por_clk) begin
+	int_rst <= 1'd0;
+end
+
+always @(posedge sys_clk) begin
+	wr <= 1'd0;
+	rd <= 1'd0;
+	if ((~sin_empty)) begin
+		wr <= 1'd1;
+		rd <= 1'd1;
+	end
+	if (sout_load) begin
+		if (sout_empty) begin
+			sout_reg[0] <= 1'd0;
+			sout_reg[8:1] <= sout_out_data;
+			sout_reg[9] <= 1'd1;
+			sout_empty <= 1'd0;
+			sout_overrun <= 1'd0;
+			sout_count <= 1'd0;
+		end else begin
+			sout_overrun <= 1'd1;
+		end
+	end
+	if (((~sout_empty) & sout_shift)) begin
+		sout_reg[8:0] <= sout_reg[9:1];
+		sout_reg[9] <= 1'd0;
+		if ((sout_count == 4'd9)) begin
+			sout_empty <= 1'd1;
+			sout_count <= 1'd0;
+		end else begin
+			sout_count <= (sout_count + 1'd1);
+		end
+	end
+	sin_sync_rx <= sin_rx;
+	sin_rx_prev <= sin_sync_rx;
+	if (sin_take) begin
+		sin_empty <= 1'd1;
+		sin_overrun <= 1'd0;
+	end
+	if (((~sin_busy) & sin_edge)) begin
+		sin_busy <= 1'd1;
+	end
+	if ((sin_shift & sin_busy)) begin
+		sin_reg[8] <= sin_sync_rx;
+		sin_reg[7:0] <= sin_reg[8:1];
+		if ((sin_count == 4'd9)) begin
+			sin_in_data <= sin_reg[8:1];
+			sin_count <= 1'd0;
+			sin_busy <= 1'd0;
+			if ((~sin_empty)) begin
+				sin_overrun <= 1'd1;
+			end else begin
+				sin_empty <= 1'd0;
+			end
+		end else begin
+			sin_count <= (sin_count + 1'd1);
+		end
+	end
+	out_counter <= 1'd0;
+	in_counter <= 1'd0;
+	if (in_active) begin
+		shift_in_strobe <= 1'd0;
+		in_counter <= (in_counter + 1'd1);
+		if ((in_counter == 9'd311)) begin
+			shift_in_strobe <= 1'd1;
+		end
+		if ((in_counter == 10'd623)) begin
+			in_counter <= 1'd0;
+		end
+	end
+	if (out_active) begin
+		shift_out_strobe <= 1'd0;
+		out_counter <= (out_counter + 1'd1);
+		if ((out_counter == 10'd623)) begin
+			out_counter <= 1'd0;
+			shift_out_strobe <= 1'd1;
+		end
+	end
+	if (sys_rst) begin
+		wr <= 1'd0;
+		rd <= 1'd0;
+		sout_empty <= 1'd1;
+		sout_overrun <= 1'd0;
+		sout_count <= 4'd0;
+		sout_reg <= 10'd0;
+		sin_in_data <= 8'd0;
+		sin_empty <= 1'd1;
+		sin_busy <= 1'd0;
+		sin_overrun <= 1'd0;
+		sin_sync_rx <= 1'd0;
+		sin_reg <= 9'd0;
+		sin_rx_prev <= 1'd0;
+		sin_count <= 4'd0;
+		shift_out_strobe <= 1'd0;
+		shift_in_strobe <= 1'd0;
+		in_counter <= 10'd0;
+		out_counter <= 10'd0;
+	end
+end
+
+endmodule
-- 
cgit v1.2.3


From 0b0faa2f1c1e0cf148a6cee37041320def12678c Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Mon, 8 Feb 2021 04:06:54 -0500
Subject: machxo2: Fill in more about mitertest.sh in README.md and clean up a
 bit.

---
 machxo2/examples/README.md | 31 +++++++++++++++++++++++++++----
 1 file changed, 27 insertions(+), 4 deletions(-)

(limited to 'machxo2/examples')

diff --git a/machxo2/examples/README.md b/machxo2/examples/README.md
index 977d6d8a..13964602 100644
--- a/machxo2/examples/README.md
+++ b/machxo2/examples/README.md
@@ -1,6 +1,5 @@
 # MachXO2 Architecture Example
-
-This contains a simple example of running `nextpnr-machxo2`:
+This directory contains a simple example of running `nextpnr-machxo2`:
 
 * `simple.sh` generates JSON output (`{pack,place,pnr}blinky.json`) of a
   classic blinky example from `blinky.v`.
@@ -22,7 +21,8 @@ This contains a simple example of running `nextpnr-machxo2`:
   and writes the resulting bitstream to MachXO2's internal flash using
   [`tinyproga`](https://github.com/tinyfpga/TinyFPGA-A-Programmer).
 
-As `nextpnr-machxo2` is developed the contents `simple.sh`, `simtest.sh`, `mitertest.sh`, and `demo.sh` are subject to change.
+As `nextpnr-machxo2` is developed the contents `simple.sh`, `simtest.sh`,
+`mitertest.sh`, and `demo.sh` are subject to change.
 
 ## How To Run
 The following applies to all `sh` scripts except `demo.sh`.
@@ -37,6 +37,29 @@ and Route phases.
 verifying the miter with either yosys' built-in SAT solver, or an external
 SMT solver.
 
+In principle, `mitertest.sh` should work in `sat` or `smt` mode with all
+example Verilog files which don't use the internal oscillator (OSCH) or other
+hard IP. However, as of this writing, only `blinky.v` passes correctly for a
+few reasons:
+
+  1. The sim models for MachXO2 primitives used by the `gate` module contain
+     `initial` values _by design_, as it matches chip behavior. Without any of
+     the following in the `gold` module (like `blinky_ext.v` currently):
+
+     * An external reset signal
+     * Internal power-on reset signal (e.g. `reg int_rst = 1'd1;`)
+     * `initial` values to manually set registers
+
+     the `gold` and `gate` modules will inherently not match.
+
+     Examples using an internal power-on reset (e.g. `uart.v`) also have issues
+     that I haven't debugged yet in both `sat` and `smt` mode.
+  2. To keep the `gold`/`gate` generation simpler, examples are currently
+     assumed to _not_ instantiate MachXO2 simulation primitives directly
+    (`FACADE_IO`, `FACADE_FF`, etc).
+  3. `synth_machxo2` runs `deminout` on `inouts` when generating the `gate`
+     module. This is not handled yet when generating the `gold` module.
+
 To keep file count lower, all yosys scripts are written inline inside the
 `sh` scripts using the `-p` option.
 
@@ -59,6 +82,7 @@ rm -rf *.dot *.json *.png *.vcd *.smt2 *.log *.txt *.bit {pack,place,pnr}*.v bli
   [the TinyFPGA Ax guide](https://tinyfpga.com/a-series-guide.html).
 * `blinky_ext.v`- Blink the LED on TinyFPA Ax using an external pin (pin 6).
 * `uart.v`- UART loopback demo at 19200 baud. Requires the following pins:
+
   * Pin 1- RX LED
   * Pin 2- TX (will echo RX)
   * Pin 3- RX
@@ -69,7 +93,6 @@ rm -rf *.dot *.json *.png *.vcd *.smt2 *.log *.txt *.bit {pack,place,pnr}*.v bli
   * Pin 8- Empty LED
 
 ## Environment Variables For Scripts
-
 * `YOSYS`- Set to the location of the `yosys` binary to test. Defaults to the
   `yosys` on the path. You may want to set this to a `yosys` binary in your
   source tree if doing development.
-- 
cgit v1.2.3


From 730e543ca65e97f1518fd0a9e692b233e15dcdbd Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Mon, 8 Feb 2021 16:55:26 -0500
Subject: machxo2: Add prefix parameter to simple.sh. Update README.md.

---
 machxo2/examples/README.md |  8 ++++----
 machxo2/examples/simple.sh | 20 ++++++++++----------
 2 files changed, 14 insertions(+), 14 deletions(-)

(limited to 'machxo2/examples')

diff --git a/machxo2/examples/README.md b/machxo2/examples/README.md
index 13964602..d4a89f7a 100644
--- a/machxo2/examples/README.md
+++ b/machxo2/examples/README.md
@@ -1,8 +1,8 @@
 # MachXO2 Architecture Example
 This directory contains a simple example of running `nextpnr-machxo2`:
 
-* `simple.sh` generates JSON output (`{pack,place,pnr}blinky.json`) of a
-  classic blinky example from `blinky.v`.
+* `simple.sh` produces nextpnr output in the files `{pack,place,pnr}*.json`,
+  as well as pre-pnr and post-pnr diagrams in `{pack,place,pnr}*.{dot, png}`.
 * `simtest.sh` will use `yosys` to generate a Verilog file from
   `{pack,place,pnr}blinky.json`, called `{pack,place,pnr}blinky.v`. It will
   then and compare `{pack,place,pnr}blinky.v`'s simulation behavior to the
@@ -10,8 +10,8 @@ This directory contains a simple example of running `nextpnr-machxo2`:
   compiler and `vvp` runtime. This is known as post-place-and-route simulation.
 * `mitertest.sh` is similar to `simtest.sh`, but more comprehensive. This
   script creates a [miter circuit](https://www21.in.tum.de/~lammich/2015_SS_Seminar_SAT/resources/Equivalence_Checking_11_30_08.pdf)
-  to compare the output port values of `{pack,place,pnr}blinky.v` against the
-  original `blinky.v` _when both modules are fed the same values on their input
+  to compare the output port values of `{pack,place,pnr}*.v` against the
+  original Verilog code _when both modules are fed the same values on their input
   ports._
 
   All possible inputs and resulting outputs can be tested in reasonable time by
diff --git a/machxo2/examples/simple.sh b/machxo2/examples/simple.sh
index c977bf1a..1da60933 100644
--- a/machxo2/examples/simple.sh
+++ b/machxo2/examples/simple.sh
@@ -1,11 +1,11 @@
 #!/usr/bin/env bash
 
-if [ $# -lt 1 ]; then
-    echo "Usage: $0 mode"
+if [ $# -lt 2 ]; then
+    echo "Usage: $0 prefix mode"
     exit -1
 fi
 
-case $1 in
+case $2 in
     "pack")
         NEXTPNR_MODE="--pack-only"
         ;;
@@ -23,12 +23,12 @@ esac
 
 set -ex
 
-${YOSYS:-yosys} -p "read_verilog blinky.v
-                    synth_machxo2 -json blinky.json
-                    show -format png -prefix blinky"
-${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --no-iobs --json blinky.json --write ${1}blinky.json
+${YOSYS:-yosys} -p "read_verilog ${1}.v
+                    synth_machxo2 -json ${1}.json
+                    show -format png -prefix ${1}"
+${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --no-iobs --json ${1}.json --write ${2}${1}.json
 ${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
-                    read_json ${1}blinky.json
+                    read_json ${2}${1}.json
                     clean -purge
-                    show -format png -prefix ${1}blinky
-                    write_verilog -noattr -norename ${1}blinky.v"
+                    show -format png -prefix ${2}${1}
+                    write_verilog -noattr -norename ${2}${1}.v"
-- 
cgit v1.2.3


From 3dbd5b0932d4851ac6c3cddf63ed0d6642d3c842 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Mon, 8 Feb 2021 17:22:09 -0500
Subject: machxo2: Add prefix parameter to simtest.sh. Remove show command from
 simtest.sh. Update README.md.

---
 machxo2/examples/.gitignore |  2 +-
 machxo2/examples/README.md  | 54 ++++++++++++++++++++++-----------------------
 machxo2/examples/simtest.sh | 27 +++++++++++++----------
 3 files changed, 43 insertions(+), 40 deletions(-)

(limited to 'machxo2/examples')

diff --git a/machxo2/examples/.gitignore b/machxo2/examples/.gitignore
index 955c6e29..8a87cc8d 100644
--- a/machxo2/examples/.gitignore
+++ b/machxo2/examples/.gitignore
@@ -1,4 +1,4 @@
-/blinky_simtest
+*_simtest*
 *.vcd
 *.png
 *.log
diff --git a/machxo2/examples/README.md b/machxo2/examples/README.md
index d4a89f7a..3542da70 100644
--- a/machxo2/examples/README.md
+++ b/machxo2/examples/README.md
@@ -3,11 +3,11 @@ This directory contains a simple example of running `nextpnr-machxo2`:
 
 * `simple.sh` produces nextpnr output in the files `{pack,place,pnr}*.json`,
   as well as pre-pnr and post-pnr diagrams in `{pack,place,pnr}*.{dot, png}`.
-* `simtest.sh` will use `yosys` to generate a Verilog file from
-  `{pack,place,pnr}blinky.json`, called `{pack,place,pnr}blinky.v`. It will
-  then and compare `{pack,place,pnr}blinky.v`'s simulation behavior to the
-  original verilog file (`blinky.v`) using the [`iverilog`](http://iverilog.icarus.com)
-  compiler and `vvp` runtime. This is known as post-place-and-route simulation.
+* `simtest.sh` extends `simple.sh` by generating `{pack,place,pnr}*.v` from
+  `{pack,place,pnr}*.json`. The script calls the [`iverilog`](http://iverilog.icarus.com)
+  compiler and `vvp` runtime to compare the behavior of `{pack,place,pnr}*.v`
+  and the original Verilog input (using a testbench `*_tb.v`). This is known as
+  post-place-and-route simulation.
 * `mitertest.sh` is similar to `simtest.sh`, but more comprehensive. This
   script creates a [miter circuit](https://www21.in.tum.de/~lammich/2015_SS_Seminar_SAT/resources/Equivalence_Checking_11_30_08.pdf)
   to compare the output port values of `{pack,place,pnr}*.v` against the
@@ -25,18 +25,33 @@ As `nextpnr-machxo2` is developed the contents `simple.sh`, `simtest.sh`,
 `mitertest.sh`, and `demo.sh` are subject to change.
 
 ## How To Run
-The following applies to all `sh` scripts except `demo.sh`.
+Each script requires a prefix that matches one of the self-contained Verilog
+examples in this directory. For instance, to create a bitstream from
+`tinyfpga.v`, use `demo.sh tinyfpga` (the `*` glob used throughout this file
+is filled with the the prefix).
 
-Each `sh` script runs yosys and nextpnr to validate a blinky design in various
-ways. The `mode` argument to each script- `pack`, `place`, or `pnr`- stop
-`nextpnr-machxo2` after the specified phase and writes out a JSON file of the
-results in `{pack,place,pnr}blinky.json`; `pnr` runs all of the Pack, Place,
-and Route phases.
+Each of `simple.sh`, `simtest.sh`, and `mitertest.sh` runs yosys and nextpnr
+to validate a Verilog design in various ways. They require an additional `mode`
+argument- `pack`, `place`, or `pnr`- which stops `nextpnr-machxo2` after the
+specified phase and writes out a JSON file of the results in
+`{pack,place,pnr}*.json`; `pnr` runs all of the Pack, Place, and Route phases.
 
-`mitertest.sh` requires an additional option- `sat` or `smt`- to choose between
+`mitertest.sh` requires an third option- `sat` or `smt`- to choose between
 verifying the miter with either yosys' built-in SAT solver, or an external
 SMT solver.
 
+Each script will exit if it finds an input Verilog example it knows it can't
+handle. To keep file count lower, all yosys scripts are written inline inside
+the `sh` scripts using the `-p` option.
+
+### Clean
+To clean output files from _all_ scripts, run:
+
+```
+rm -rf *.dot *.json *.png *.vcd *.smt2 *.log *.txt *.bit {pack,place,pnr}*.v *_simtest*
+```
+
+## Known Issues
 In principle, `mitertest.sh` should work in `sat` or `smt` mode with all
 example Verilog files which don't use the internal oscillator (OSCH) or other
 hard IP. However, as of this writing, only `blinky.v` passes correctly for a
@@ -60,21 +75,6 @@ few reasons:
   3. `synth_machxo2` runs `deminout` on `inouts` when generating the `gate`
      module. This is not handled yet when generating the `gold` module.
 
-To keep file count lower, all yosys scripts are written inline inside the
-`sh` scripts using the `-p` option.
-
-`demo.sh` requires a prefix that matches one of the self-contained Verilog
-examples in this directory. For instance, to create a bitstream from
-`tinyfpga.v`, use `demo.sh tinyfpga`. The script will catch Verilog files which
-are not meant to be programmed onto TinyFPA Ax.
-
-### Clean
-To clean output files from _all_ scripts, run:
-
-```
-rm -rf *.dot *.json *.png *.vcd *.smt2 *.log *.txt *.bit {pack,place,pnr}*.v blinky_simtest*
-```
-
 ## Verilog Examples
 * `blinky.v`/`blinky_tb.v`- A blinky example meant for simulation.
 * `tinyfpga.v`- Blink the LED on TinyFPA Ax.
diff --git a/machxo2/examples/simtest.sh b/machxo2/examples/simtest.sh
index 53f2e728..2c7f6f30 100644
--- a/machxo2/examples/simtest.sh
+++ b/machxo2/examples/simtest.sh
@@ -1,11 +1,11 @@
 #!/usr/bin/env bash
 
-if [ $# -lt 1 ]; then
-    echo "Usage: $0 mode"
+if [ $# -lt 2 ]; then
+    echo "Usage: $0 prefix mode"
     exit -1
 fi
 
-case $1 in
+case $2 in
     "pack")
         NEXTPNR_MODE="--pack-only"
         ;;
@@ -21,16 +21,19 @@ case $1 in
         ;;
 esac
 
+if [ ! -f ${1}_tb.v ]; then
+    echo "No testbench file (${1}_tb.v) found for ${1}.v"
+    exit -3
+fi
+
 set -ex
 
-${YOSYS:-yosys} -p "read_verilog blinky.v
-                    synth_machxo2 -json blinky.json
-                    show -format png -prefix blinky"
-${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --no-iobs --json blinky.json --write ${1}blinky.json
+${YOSYS:-yosys} -p "read_verilog ${1}.v
+                    synth_machxo2 -json ${1}.json"
+${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --no-iobs --json ${1}.json --write ${2}${1}.json
 ${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
-                    read_json ${1}blinky.json
+                    read_json ${2}${1}.json
                     clean -purge
-                    show -format png -prefix ${1}blinky
-                    write_verilog -noattr -norename ${1}blinky.v"
-iverilog -o blinky_simtest ${CELLS_SIM:-`${YOSYS:yosys}-config --datdir/machxo2/cells_sim.v`} blinky_tb.v ${1}blinky.v
-vvp -N ./blinky_simtest
+                    write_verilog -noattr -norename ${2}${1}.v"
+iverilog -o ${1}_simtest ${CELLS_SIM:-`${YOSYS:yosys}-config --datdir/machxo2/cells_sim.v`} ${1}_tb.v ${2}${1}.v
+vvp -N ./${1}_simtest
-- 
cgit v1.2.3