From 510969ab9704865f87c7c0bd09e0185b729feffc Mon Sep 17 00:00:00 2001
From: gatecat <gatecat@ds0.me>
Date: Thu, 11 Feb 2021 11:10:32 +0000
Subject: Create machxo2 backend (renamed from generic).

Signed-off-by: William D. Jones <thor0505@comcast.net>
---
 machxo2/synth/cells_map.v       | 12 ++++++++
 machxo2/synth/prims.v           | 67 +++++++++++++++++++++++++++++++++++++++++
 machxo2/synth/synth_machxo2.tcl | 24 +++++++++++++++
 3 files changed, 103 insertions(+)
 create mode 100644 machxo2/synth/cells_map.v
 create mode 100644 machxo2/synth/prims.v
 create mode 100644 machxo2/synth/synth_machxo2.tcl

(limited to 'machxo2/synth')

diff --git a/machxo2/synth/cells_map.v b/machxo2/synth/cells_map.v
new file mode 100644
index 00000000..1d0939e0
--- /dev/null
+++ b/machxo2/synth/cells_map.v
@@ -0,0 +1,12 @@
+module \$lut (A, Y);
+	parameter WIDTH = 0;
+	parameter LUT = 0;
+	input [WIDTH-1:0] A;
+	output Y;
+
+	localparam rep = 1<<(`LUT_K-WIDTH);
+
+	LUT #(.K(`LUT_K), .INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.I(A), .Q(Y));
+endmodule
+
+module  \$_DFF_P_ (input D, C, output Q); DFF  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
diff --git a/machxo2/synth/prims.v b/machxo2/synth/prims.v
new file mode 100644
index 00000000..ca445e6e
--- /dev/null
+++ b/machxo2/synth/prims.v
@@ -0,0 +1,67 @@
+// LUT and DFF are combined to a GENERIC_SLICE
+
+module LUT #(
+	parameter K = 4,
+	parameter [2**K-1:0] INIT = 0
+) (
+	input [K-1:0] I,
+	output Q
+);
+	wire [K-1:0] I_pd;
+
+	genvar ii;
+	generate
+		for (ii = 0; ii < K; ii = ii + 1'b1)
+			assign I_pd[ii] = (I[ii] === 1'bz) ? 1'b0 : I[ii];
+	endgenerate
+
+	assign Q = INIT[I_pd];
+endmodule
+
+module DFF (
+	input CLK, D,
+	output reg Q
+);
+	initial Q = 1'b0;
+	always @(posedge CLK)
+		Q <= D;
+endmodule
+
+module GENERIC_SLICE #(
+	parameter K = 4,
+	parameter [2**K-1:0] INIT = 0,
+	parameter FF_USED = 1'b0
+) (
+	input CLK,
+	input [K-1:0] I,
+	output F,
+	output Q
+);
+	wire f_wire;
+	
+	LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(f_wire));
+
+	DFF dff_i(.CLK(CLK), .D(f_wire), .Q(Q));
+
+	assign F = f_wire;
+endmodule
+
+module GENERIC_IOB #(
+	parameter INPUT_USED = 1'b0,
+	parameter OUTPUT_USED = 1'b0,
+	parameter ENABLE_USED = 1'b0
+) (
+	inout PAD,
+	input I, EN,
+	output O
+);
+	generate if (OUTPUT_USED && ENABLE_USED)
+		assign PAD = EN ? I : 1'bz;
+	else if (OUTPUT_USED)
+		assign PAD = I;
+	endgenerate
+
+	generate if (INPUT_USED)
+		assign O = PAD;
+	endgenerate
+endmodule
diff --git a/machxo2/synth/synth_machxo2.tcl b/machxo2/synth/synth_machxo2.tcl
new file mode 100644
index 00000000..e5d88e0d
--- /dev/null
+++ b/machxo2/synth/synth_machxo2.tcl
@@ -0,0 +1,24 @@
+# Usage
+# tcl synth_generic.tcl {K} {out.json}
+
+set LUT_K 4
+if {$argc > 0} { set LUT_K [lindex $argv 0] }
+yosys read_verilog -lib [file dirname [file normalize $argv0]]/prims.v
+yosys hierarchy -check
+yosys proc
+yosys flatten
+yosys tribuf -logic
+yosys deminout
+yosys synth -run coarse
+yosys memory_map
+yosys opt -full
+yosys techmap -map +/techmap.v
+yosys opt -fast
+yosys abc -lut $LUT_K -dress
+yosys clean
+yosys techmap -D LUT_K=$LUT_K -map [file dirname [file normalize $argv0]]/cells_map.v
+yosys clean
+yosys hierarchy -check
+yosys stat
+
+if {$argc > 1} { yosys write_json [lindex $argv 1] }
-- 
cgit v1.2.3