From 9221acc9e211766d79d7c7dde5d5fc8bb053354d Mon Sep 17 00:00:00 2001 From: gatecat Date: Sat, 15 May 2021 10:26:27 +0100 Subject: mistral: Fix ENA and ACLR bitstream generation Signed-off-by: gatecat --- mistral/bitstream.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'mistral/bitstream.cc') diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc index 2c7f7862..e31b94af 100644 --- a/mistral/bitstream.cc +++ b/mistral/bitstream.cc @@ -283,7 +283,7 @@ struct MistralBitgen if (get_net_or_empty(ff, id_ENA) != nullptr) { // not using ffInfo.ctrlset, this has a fake net always to // ensure different constants don't collide cv->bmux_b_set(CycloneV::LAB, pos, en_en[ce_idx], 0, true); - cv->bmux_b_set(CycloneV::LAB, pos, en_ninv[ce_idx], 0, !ff->ffInfo.ctrlset.ena.inverted); + cv->bmux_b_set(CycloneV::LAB, pos, en_ninv[ce_idx], 0, ff->ffInfo.ctrlset.ena.inverted); } else { cv->bmux_b_set(CycloneV::LAB, pos, en_en[ce_idx], 0, false); } @@ -315,7 +315,7 @@ struct MistralBitgen const std::array aclr_inp{CycloneV::ACLR0_SEL, CycloneV::ACLR1_SEL}; for (int i = 0; i < 2; i++) { // Quartus seems to set unused ACLRs to CLKI2... - if (ctx->getBoundWireNet(lab_data.aclr_wires[i]) == nullptr) + if (!lab_data.aclr_used[i]) cv->bmux_m_set(CycloneV::LAB, pos, aclr_inp[i], 0, CycloneV::CLKI2); else cv->bmux_m_set(CycloneV::LAB, pos, aclr_inp[i], 0, (i == 1) ? CycloneV::GIN0 : CycloneV::GIN1); -- cgit v1.2.3