From ddb084e9a8a0cba10536951236cde824526e8071 Mon Sep 17 00:00:00 2001 From: gatecat Date: Sun, 19 Dec 2021 16:41:34 +0000 Subject: archapi: Use arbitrary rather than actual placement in predictDelay This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat --- nexus/arch.cc | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to 'nexus/arch.cc') diff --git a/nexus/arch.cc b/nexus/arch.cc index 74a06478..a7751425 100644 --- a/nexus/arch.cc +++ b/nexus/arch.cc @@ -603,16 +603,14 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const int dist_y = std::abs(src_y - dst_y); return 75 * dist_x + 75 * dist_y + 250; } -delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const +delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const { - if (net_info->driver.cell == nullptr || net_info->driver.cell->bel == BelId() || sink.cell->bel == BelId()) + NPNR_UNUSED(src_pin); + if (dst_pin == id_FCI) return 0; - if (sink.port == id_FCI) - return 0; - int src_x = net_info->driver.cell->bel.tile % chip_info->width, - src_y = net_info->driver.cell->bel.tile / chip_info->width; + int src_x = src_bel.tile % chip_info->width, src_y = src_bel.tile / chip_info->width; - int dst_x = sink.cell->bel.tile % chip_info->width, dst_y = sink.cell->bel.tile / chip_info->width; + int dst_x = dst_bel.tile % chip_info->width, dst_y = dst_bel.tile / chip_info->width; int dist_x = std::abs(src_x - dst_x); int dist_y = std::abs(src_y - dst_y); return 100 * dist_x + 100 * dist_y + 250; -- cgit v1.2.3