From 44f98c545b353c823692f91953c1ca74b6be2d4f Mon Sep 17 00:00:00 2001 From: David Shah Date: Sun, 12 Jan 2020 20:44:22 +0000 Subject: nexus: Add global networks Signed-off-by: David Shah --- nexus/arch.cc | 3 +++ nexus/arch.h | 5 +++-- nexus/constids.inc | 5 +++++ 3 files changed, 11 insertions(+), 2 deletions(-) (limited to 'nexus') diff --git a/nexus/arch.cc b/nexus/arch.cc index b0a22894..663941ff 100644 --- a/nexus/arch.cc +++ b/nexus/arch.cc @@ -382,6 +382,9 @@ bool Arch::place() if (placer == "heap") { PlacerHeapCfg cfg(getCtx()); + cfg.ioBufTypes.insert(id_SEIO33_CORE); + cfg.ioBufTypes.insert(id_SEIO18_CORE); + cfg.ioBufTypes.insert(id_OSC_CORE); cfg.criticalityExponent = 7; if (!placer_heap(getCtx(), cfg)) return false; diff --git a/nexus/arch.h b/nexus/arch.h index 9a92d9af..f0f51271 100644 --- a/nexus/arch.h +++ b/nexus/arch.h @@ -362,7 +362,7 @@ inline bool chip_branch_tile(const ChipInfoPOD *chip, int32_t x, int32_t y, int3 int32_t branch_x; if (!chip_get_branch_loc(chip, x, branch_x)) return false; - next = chip_tile_from_xy(chip, x, y); + next = chip_tile_from_xy(chip, branch_x, y); return true; } inline bool chip_rel_loc_tile(const ChipInfoPOD *chip, int32_t base, const RelWireInfoPOD &rel, int32_t &next) @@ -1258,7 +1258,8 @@ struct Arch : BaseCtx } inline WireId canonical_wire(int32_t tile, uint16_t index) const { - return chip_canonical_wire(db, chip_info, tile, index); + WireId c = chip_canonical_wire(db, chip_info, tile, index); + return c; } IdString pip_src_wire_name(PipId pip) const { diff --git a/nexus/constids.inc b/nexus/constids.inc index 8a7d688e..edde3bc9 100644 --- a/nexus/constids.inc +++ b/nexus/constids.inc @@ -103,3 +103,8 @@ X(CIB_T) X(CIB_LR) X(IO_TYPE) + +X(OSC_CORE) +X(HFCLKOUT) +X(LFCLKOUT) + -- cgit v1.2.3