/* * nextpnr -- Next Generation Place and Route * * Copyright (C) 2018 Clifford Wolf * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #ifndef DESIGN_H #define DESIGN_H #ifndef NEXTPNR_H #error Include "design.h" via "nextpnr.h" only. #endif NEXTPNR_NAMESPACE_BEGIN struct CellInfo; struct PortRef { CellInfo *cell = nullptr; IdString port; }; struct NetInfo { IdString name; PortRef driver; std::vector users; std::unordered_map attrs; // wire -> uphill_pip std::unordered_map wires; }; enum PortType { PORT_IN = 0, PORT_OUT = 1, PORT_INOUT = 2 }; struct PortInfo { IdString name; NetInfo *net; PortType type; }; struct CellInfo { IdString name, type; std::unordered_map ports; std::unordered_map attrs, params; BelId bel; // cell_port -> bel_pin std::unordered_map pins; }; struct Design { struct Chip chip; Design(ChipArgs args) : chip(args) { // ... } std::unordered_map nets; std::unordered_map cells; }; NEXTPNR_NAMESPACE_END #endif