diff options
| author | Clifford Wolf <clifford@clifford.at> | 2016-03-29 09:53:35 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-03-29 09:53:35 +0200 |
| commit | d4472ae9453c3eb713e2260b198d0236632a60b7 (patch) | |
| tree | eebd7258a2720fffb038516ee8754e1550c0eb09 | |
| parent | 95784437ac237be981d0cf573386ba22f28f9624 (diff) | |
| parent | 75f0030458a6c5e37238e2437ea469ba9dfd389b (diff) | |
| download | yosys-d4472ae9453c3eb713e2260b198d0236632a60b7.tar.gz yosys-d4472ae9453c3eb713e2260b198d0236632a60b7.tar.bz2 yosys-d4472ae9453c3eb713e2260b198d0236632a60b7.zip | |
Merge pull request #141 from azonenberg/master
Add Greenpak4 SYSRESET block support
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 6b5100f75..3acea01d2 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -104,3 +104,12 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT); //more complex hard IP blocks are not supported for simulation yet endmodule + +//keep constraint needed to prevent optimization since we have no outputs +(* keep *) +module GP_SYSRESET(input RST); + parameter RESET_MODE = "RISING"; + + //cannot simulate whole system reset + +endmodule |