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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-04 15:19:24 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-04 15:40:07 +0200 |
| commit | b5a3419ac2c6f367b90f062c4e2252029910cdb9 (patch) | |
| tree | bbc318d91ef1f5b8ba1117b3f317cce007236d0b /README | |
| parent | ebbbe7fc8360ca0bd8f840d3df1b77ab2fb569b6 (diff) | |
| download | yosys-b5a3419ac2c6f367b90f062c4e2252029910cdb9.tar.gz yosys-b5a3419ac2c6f367b90f062c4e2252029910cdb9.tar.bz2 yosys-b5a3419ac2c6f367b90f062c4e2252029910cdb9.zip | |
Added support for non-standard "module mod_name(...);" syntax
Diffstat (limited to 'README')
| -rw-r--r-- | README | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -276,6 +276,11 @@ Verilog Attributes and non-standard features for everything that comes after the {* ... *} statement. (Reset by adding an empty {* *} statement.) +- Modules can be declared with "module mod_name(...);" (with three dots + instead of a list of moudle ports). With this syntax it is sufficient + to simply declare a module port as 'input' or 'output' in the module + body. + - Sized constants (the syntax <size>'s?[bodh]<value>) support constant expressions as <size>. If the expresion is not a simple identifier, it must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010 |