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author | Jim Lawson <ucbjrl@berkeley.edu> | 2018-08-27 10:09:39 -0700 |
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committer | GitHub <noreply@github.com> | 2018-08-27 10:09:39 -0700 |
commit | 604b5d4e2026ffcb726ed65e4edbc6dbcec5f64f (patch) | |
tree | 024214903fdf08578b38478be42b820abc09140b /frontends/ast/ast.h | |
parent | 2c0601eb6f2c5ed0d376ed880efda48a2aeeb9ef (diff) | |
parent | ddc1761f1a443ea9560c67cfc126160ba7254a39 (diff) | |
download | yosys-604b5d4e2026ffcb726ed65e4edbc6dbcec5f64f.tar.gz yosys-604b5d4e2026ffcb726ed65e4edbc6dbcec5f64f.tar.bz2 yosys-604b5d4e2026ffcb726ed65e4edbc6dbcec5f64f.zip |
Merge pull request #3 from YosysHQ/master
merge with YosysHQ
Diffstat (limited to 'frontends/ast/ast.h')
-rw-r--r-- | frontends/ast/ast.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index d94199643..7e97bdb3b 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -274,7 +274,7 @@ namespace AST }; // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code - void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit, + void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire); // parametric modules are supported directly by the AST library @@ -305,7 +305,7 @@ namespace AST namespace AST_INTERNAL { // internal state variables - extern bool flag_dump_ast1, flag_dump_ast2, flag_dump_rtlil, flag_nolatches, flag_nomeminit; + extern bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_rtlil, flag_nolatches, flag_nomeminit; extern bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire; extern AST::AstNode *current_ast, *current_ast_mod; extern std::map<std::string, AST::AstNode*> current_scope; |