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| author | Jim Lawson <ucbjrl@berkeley.edu> | 2018-08-27 12:13:04 -0700 |
|---|---|---|
| committer | Jim Lawson <ucbjrl@berkeley.edu> | 2018-08-27 12:13:04 -0700 |
| commit | e217c6c52fd26793c3ca8ae0a57e82344fe3f795 (patch) | |
| tree | d43ae55bf739b20ee66031e3906ddf0136f87800 /frontends/verilog/.gitignore | |
| parent | 380c6f0e978869099d5b2c5dd81d8065a1f5c3cc (diff) | |
| parent | 604b5d4e2026ffcb726ed65e4edbc6dbcec5f64f (diff) | |
| download | yosys-e217c6c52fd26793c3ca8ae0a57e82344fe3f795.tar.gz yosys-e217c6c52fd26793c3ca8ae0a57e82344fe3f795.tar.bz2 yosys-e217c6c52fd26793c3ca8ae0a57e82344fe3f795.zip | |
Merge branch 'master' into firrtl+modules+shiftfixes
Diffstat (limited to 'frontends/verilog/.gitignore')
| -rw-r--r-- | frontends/verilog/.gitignore | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verilog/.gitignore b/frontends/verilog/.gitignore index 1d4ae9e5c..aadbcdcdd 100644 --- a/frontends/verilog/.gitignore +++ b/frontends/verilog/.gitignore @@ -1,4 +1,4 @@ verilog_lexer.cc verilog_parser.output verilog_parser.tab.cc -verilog_parser.tab.h +verilog_parser.tab.hh |