diff options
| author | georgerennie <georgerennie@gmail.com> | 2020-12-01 01:37:19 +0000 |
|---|---|---|
| committer | georgerennie <georgerennie@gmail.com> | 2020-12-01 01:37:19 +0000 |
| commit | c1f6ce8b33b1c06a4e38b621e27876d5715eb26d (patch) | |
| tree | ef64f8bd35b8ed518ba347b91ef41494e4d15527 /frontends/verilog/verilog_frontend.cc | |
| parent | 2116c585810cddb73777b46ea9aad0d6d511d82b (diff) | |
| download | yosys-c1f6ce8b33b1c06a4e38b621e27876d5715eb26d.tar.gz yosys-c1f6ce8b33b1c06a4e38b621e27876d5715eb26d.tar.bz2 yosys-c1f6ce8b33b1c06a4e38b621e27876d5715eb26d.zip | |
Fix SYNTHESIS always being defined in Verilog frontend
Diffstat (limited to 'frontends/verilog/verilog_frontend.cc')
| -rw-r--r-- | frontends/verilog/verilog_frontend.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 2e9c9b2e2..5319a45ad 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -446,6 +446,9 @@ struct VerilogFrontend : public Frontend { } break; } + + defines_map.add(formal_mode ? "FORMAL" : "SYNTHESIS", "1"); + extra_args(f, filename, args, argidx); log_header(design, "Executing Verilog-2005 frontend: %s\n", filename.c_str()); |