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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-02 19:08:02 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-02 19:08:02 +0200 |
| commit | 8e7361f128ce00a742412931efcf7cbe5795a39a (patch) | |
| tree | c3dc8f179ba5c9b5ce0ea9791d37476d42d26dde /passes | |
| parent | 04727c7e0fb4c00b38999da192e4ada2a6f9474a (diff) | |
| download | yosys-8e7361f128ce00a742412931efcf7cbe5795a39a.tar.gz yosys-8e7361f128ce00a742412931efcf7cbe5795a39a.tar.bz2 yosys-8e7361f128ce00a742412931efcf7cbe5795a39a.zip | |
Removed at() method from RTLIL::IdString
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/sat/expose.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index affd685e4..e856fdf76 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -50,7 +50,7 @@ static bool consider_cell(RTLIL::Design *design, std::set<RTLIL::IdString> &dff_ { if (cell->name[0] == '$' || dff_cells.count(cell->name)) return false; - if (cell->type.at(0) == '\\' && !design->modules_.count(cell->type)) + if (cell->type[0] == '\\' && !design->modules_.count(cell->type)) return false; return true; } |