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authorDavid Shah <davey1576@gmail.com>2018-07-13 14:32:23 +0200
committerDavid Shah <davey1576@gmail.com>2018-07-13 14:32:23 +0200
commiteb8f3f7dc467156ffaec0ed1a471fe5e610709c7 (patch)
treedeeb75ddfbf74dc42b5d9664b6d3f1b32d164ca1 /techlibs/ecp5/cells_sim.v
parent1def34f2a64603a3186dc50460fe964f1f197a43 (diff)
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ecp5: Adding DFF maps
Signed-off-by: David Shah <davey1576@gmail.com>
Diffstat (limited to 'techlibs/ecp5/cells_sim.v')
-rw-r--r--techlibs/ecp5/cells_sim.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 06e6133a7..32aec4e93 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -199,7 +199,7 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
wire srval = (REGSET == "SET") ? 1'b1 : 1'b0;
- initial Q = 1'b0;
+ initial Q = srval;
generate
if (SRMODE == "ASYNC") begin