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| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-30 14:58:25 +0100 |
|---|---|---|
| committer | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-30 14:58:25 +0100 |
| commit | df8390f5df9868b583ce88a4d2ce41511fab2f7b (patch) | |
| tree | 55088678a5ae2860f6ab39b9e6be3f7bcdc18d05 /tests/arch/gowin | |
| parent | 0f6269b04c4a5f44b62021759507bcbe61a7c8d7 (diff) | |
| download | yosys-df8390f5df9868b583ce88a4d2ce41511fab2f7b.tar.gz yosys-df8390f5df9868b583ce88a4d2ce41511fab2f7b.tar.bz2 yosys-df8390f5df9868b583ce88a4d2ce41511fab2f7b.zip | |
don't cound exact luts in big muxes; futile and fragile
Diffstat (limited to 'tests/arch/gowin')
| -rw-r--r-- | tests/arch/gowin/mux.ys | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys index 1cb3d53e6..f7e478c87 100644 --- a/tests/arch/gowin/mux.ys +++ b/tests/arch/gowin/mux.ys @@ -30,7 +30,6 @@ proc equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module -select -assert-count 5 t:LUT4 select -assert-count 11 t:IBUF select -assert-count 1 t:OBUF @@ -42,8 +41,6 @@ proc equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 10 t:LUT4 -select -assert-count 1 t:LUT3 select -assert-count 20 t:IBUF select -assert-count 1 t:OBUF |