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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-12-28 16:22:24 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-12-28 16:22:24 +0100 |
| commit | a82c701668d8197c01e54cb68bc45f2278f3172f (patch) | |
| tree | cf7a692d2a470c5e045caa9a9bb8a0a6e8886880 /tests/arch/xilinx/fsm.ys | |
| parent | 509da7ed1a1e27066451f57868108b473cf516a0 (diff) | |
| download | yosys-a82c701668d8197c01e54cb68bc45f2278f3172f.tar.gz yosys-a82c701668d8197c01e54cb68bc45f2278f3172f.tar.bz2 yosys-a82c701668d8197c01e54cb68bc45f2278f3172f.zip | |
Make test without iopads
Diffstat (limited to 'tests/arch/xilinx/fsm.ys')
| -rw-r--r-- | tests/arch/xilinx/fsm.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys index f03400fe7..3235d5af3 100644 --- a/tests/arch/xilinx/fsm.ys +++ b/tests/arch/xilinx/fsm.ys @@ -3,7 +3,7 @@ hierarchy -top fsm proc flatten -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad miter -equiv -make_assert -flatten gold gate miter sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter |